From cd7ea29ce604637d7160025c003d639ca7033631 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Wed, 21 Apr 2021 16:03:42 -0400 Subject: [PATCH 1/2] buildroot: add workaround for weird initial MSTATUS state --- wally-pipelined/testbench/testbench-busybear.sv | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 25c21747..0f5c9e2f 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -299,11 +299,13 @@ module testbench_busybear(); `ERROR \ end \ end else begin \ - for(integer j=0; j Date: Wed, 21 Apr 2021 16:06:27 -0500 Subject: [PATCH 2/2] Fixed most relevant remaining synthesis compilation warnings with Ben --- wally-pipelined/src/fpu/fpu.sv | 6 ++++-- wally-pipelined/src/fpu/fpuaddcvt2.sv | 1 + wally-pipelined/src/ifu/icache.sv | 2 +- wally-pipelined/src/ifu/ifu.sv | 2 +- wally-pipelined/src/muldiv/div.sv | 3 ++- wally-pipelined/src/muldiv/muldiv.sv | 1 + 6 files changed, 10 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index ef38e43c..b26be58d 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -41,8 +41,8 @@ module fpu ( //temporarily assign pipe clear and enable signals //to never flush & always be running - assign PipeClear = 1'b0; - assign PipeEnable = 1'b1; + localparam PipeClear = 1'b0; + localparam PipeEnable = 1'b1; always_comb begin PipeEnableDE = PipeEnable; @@ -154,6 +154,7 @@ module fpu ( logic [10:0] AddExpPostSumE; logic AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE, AddOpBNormE, AddInvalidE; logic AddDenormInE, AddSwapE, AddNormOvflowE, AddSignAE; + logic AddConvertE; logic [63:0] AddFloat1E, AddFloat2E; logic [10:0] AddExp1DenormE, AddExp2DenormE, AddExponentE; logic [63:0] AddOp1E, AddOp2E; @@ -310,6 +311,7 @@ module fpu ( logic [10:0] AddExpPostSumM; logic AddCorrSignM, AddOp1NormM, AddOp2NormM, AddOpANormM, AddOpBNormM, AddInvalidM; logic AddDenormInM, AddSwapM, AddNormOvflowM, AddSignAM; + logic AddConvertM, AddSignM; logic [63:0] AddFloat1M, AddFloat2M; logic [10:0] AddExp1DenormM, AddExp2DenormM, AddExponentM; logic [63:0] AddOp1M, AddOp2M; diff --git a/wally-pipelined/src/fpu/fpuaddcvt2.sv b/wally-pipelined/src/fpu/fpuaddcvt2.sv index 66cb5f6c..32dc3ac8 100755 --- a/wally-pipelined/src/fpu/fpuaddcvt2.sv +++ b/wally-pipelined/src/fpu/fpuaddcvt2.sv @@ -64,6 +64,7 @@ module fpuaddcvt2 (AddResultM, AddFlagsM, AddDenormM, AddSumM, AddSumTcM, AddSel wire [63:0] Result; wire [63:0] sum_norm, sum_norm_w_bypass; wire [5:0] norm_shift, norm_shift_denorm; + wire exp_valid; wire DenormIO; wire [4:0] FlagsIn; wire Sticky_out; diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv index 10f52b59..ca771e40 100644 --- a/wally-pipelined/src/ifu/icache.sv +++ b/wally-pipelined/src/ifu/icache.sv @@ -57,7 +57,7 @@ module icache( logic [`XLEN-1:0] LastReadDataF, LastReadAdrF, InDataF; // instruction for NOP - logic [31:0] nop = 32'h00000013; + localparam [31:0] nop = 32'h00000013; // Temporary change to bridge the new interface to old behaviors logic [`XLEN-1:0] PCPF; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index d5ecf470..4865b676 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -73,7 +73,7 @@ module ifu ( logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkM, PCPF; logic CompressedF; logic [31:0] InstrRawD, InstrE, InstrW; - logic [31:0] nop = 32'h00000013; // instruction for NOP + localparam [31:0] nop = 32'h00000013; // instruction for NOP // *** send this to the trap unit logic ITLBPageFaultF; diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv index 78aea323..05c9793a 100755 --- a/wally-pipelined/src/muldiv/div.sv +++ b/wally-pipelined/src/muldiv/div.sv @@ -46,7 +46,8 @@ module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start); logic [64:0] Qd, Rd, Qd2, Rd2; logic [3:0] quotient; logic otfzero; - logic shiftResult; + logic shiftResult; + logic enablev, state0v, donev, divdonev, oftzerov, divBusyv, ulp; // Divider goes the distance to 37 cycles // (thanks the evil divisor for D = 0x1) diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv index c61b02c4..8d661992 100644 --- a/wally-pipelined/src/muldiv/muldiv.sv +++ b/wally-pipelined/src/muldiv/muldiv.sv @@ -55,6 +55,7 @@ module muldiv ( logic enable_q, gclk; logic [2:0] Funct3E_Q; + logic div0error; // Multiplier