From e29803be304464f0faa4c3a2ed3d3e713f7d3db0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 28 Dec 2021 16:14:10 -0600 Subject: [PATCH] Removed CommittedM as it is redundant with LSUStall. --- wally-pipelined/src/cache/dcache.sv | 2 -- wally-pipelined/src/cache/dcachefsm.sv | 15 --------------- wally-pipelined/src/lsu/lsu.sv | 15 +-------------- wally-pipelined/src/privileged/privileged.sv | 4 ++-- wally-pipelined/src/privileged/trap.sv | 6 +++--- wally-pipelined/src/wally/wallypipelinedhart.sv | 5 ++--- 6 files changed, 8 insertions(+), 39 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 0cd5d394..b1969306 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -42,7 +42,6 @@ module dcache input logic [`XLEN-1:0] FinalWriteDataM, output logic [`XLEN-1:0] ReadDataWordM, output logic DCacheStall, - output logic CommittedM, output logic DCacheMiss, output logic DCacheAccess, @@ -282,7 +281,6 @@ module dcache .CacheHit, .VictimDirty, .DCacheStall, - .CommittedM, .DCacheMiss, .DCacheAccess, .SelAdrM, diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index d45d92e3..5fa2395b 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -46,7 +46,6 @@ module dcachefsm // hazard outputs output logic DCacheStall, - output logic CommittedM, // counter outputs output logic DCacheMiss, output logic DCacheAccess, @@ -115,7 +114,6 @@ module dcachefsm ClearDirty = 1'b0; SRAMWordWriteEnableM = 1'b0; SRAMBlockWriteEnableM = 1'b0; - CommittedM = 1'b0; SelEvict = 1'b0; LRUWriteEn = 1'b0; SelFlush = 1'b0; @@ -136,7 +134,6 @@ module dcachefsm SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; - CommittedM = 1'b0; // TLB Miss if(IgnoreRequest) begin @@ -146,7 +143,6 @@ module dcachefsm // PTW ready the CPU will stall. // The page table walker asserts it's control 1 cycle // after the TLBs miss. - // CommittedM = 1'b1; ??? *** Not Sure yet. NextState = STATE_READY; end @@ -216,7 +212,6 @@ module dcachefsm STATE_MISS_FETCH_WDV: begin DCacheStall = 1'b1; SelAdrM = 2'b10; - CommittedM = 1'b1; if (BUSACK) begin NextState = STATE_MISS_FETCH_DONE; @@ -228,7 +223,6 @@ module dcachefsm STATE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 2'b10; - CommittedM = 1'b1; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; DCWriteLine = 1'b1; @@ -244,14 +238,12 @@ module dcachefsm SelAdrM = 2'b10; SetValid = 1'b1; ClearDirty = 1'b1; - CommittedM = 1'b1; //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write end STATE_MISS_READ_WORD: begin SelAdrM = 2'b10; DCacheStall = 1'b1; - CommittedM = 1'b1; if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write. NextState = STATE_MISS_WRITE_WORD; end else begin @@ -263,7 +255,6 @@ module dcachefsm STATE_MISS_READ_WORD_DELAY: begin //SelAdrM = 2'b10; - CommittedM = 1'b1; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; @@ -294,7 +285,6 @@ module dcachefsm SRAMWordWriteEnableM = 1'b1; SetDirty = 1'b1; SelAdrM = 2'b10; - CommittedM = 1'b1; LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; @@ -308,7 +298,6 @@ module dcachefsm STATE_MISS_EVICT_DIRTY: begin DCacheStall = 1'b1; SelAdrM = 2'b10; - CommittedM = 1'b1; SelEvict = 1'b1; if(BUSACK) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; @@ -319,7 +308,6 @@ module dcachefsm STATE_CPU_BUSY: begin - CommittedM = 1'b1; SelAdrM = 2'b00; if(CPUBusy) begin NextState = STATE_CPU_BUSY; @@ -331,7 +319,6 @@ module dcachefsm end STATE_CPU_BUSY_FINISH_AMO: begin - CommittedM = 1'b1; SelAdrM = 2'b10; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; @@ -349,7 +336,6 @@ module dcachefsm STATE_FLUSH: begin DCacheStall = 1'b1; - CommittedM = 1'b1; SelAdrM = 2'b11; SelFlush = 1'b1; FlushAdrCntEn = 1'b1; @@ -372,7 +358,6 @@ module dcachefsm STATE_FLUSH_WRITE_BACK: begin DCacheStall = 1'b1; SelAdrM = 2'b11; - CommittedM = 1'b1; SelFlush = 1'b1; if(BUSACK) begin NextState = STATE_FLUSH_CLEAR_DIRTY; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 8544a137..58394ed4 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -42,7 +42,6 @@ module lsu input logic ExceptionM, input logic PendingInterruptM, input logic FlushDCacheM, - output logic CommittedM, output logic SquashSCW, output logic DCacheMiss, output logic DCacheAccess, @@ -110,9 +109,6 @@ module lsu logic SelHPTW; - logic DCCommittedM; - logic CommittedMfromBus; - logic BusStall; @@ -221,7 +217,6 @@ module lsu assign CPUBusy = StallW & ~SelHPTW; // always block interrupts when using the hardware page table walker. - assign CommittedM = SelHPTW | DCCommittedM | CommittedMfromBus; // this is for the d cache SRAM. // turns out because we cannot pipeline hptw requests we don't need this register @@ -259,13 +254,13 @@ module lsu assign LsuAdrE = IEUAdrE[11:0]; assign LsuPAdrM = IEUAdrExtM; assign CPUBusy = StallW; - assign CommittedM = CommittedMfromBus; assign DTLBLoadPageFaultM = 1'b0; assign DTLBStorePageFaultM = 1'b0; end endgenerate + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .DisableTranslation(SelHPTW), @@ -369,7 +364,6 @@ module lsu .MemAdrE(DCAdrE), .MemPAdrM, .FinalWriteDataM, .ReadDataWordM, .DCacheStall, - .CommittedM(DCCommittedM), .DCacheMiss, .DCacheAccess, .IgnoreRequest, .CacheableM(CacheableM), @@ -475,7 +469,6 @@ module lsu PreCntEn = 1'b0; LsuBusWrite = 1'b0; LsuBusRead = 1'b0; - CommittedMfromBus = 1'b0; BUSACK = 1'b0; SelUncached = 1'b0; @@ -515,7 +508,6 @@ module lsu STATE_BUS_UNCACHED_WRITE : begin BusStall = 1'b1; LsuBusWrite = 1'b1; - CommittedMfromBus = 1'b1; if(LsuBusAck) begin BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; end else begin @@ -526,7 +518,6 @@ module lsu STATE_BUS_UNCACHED_READ: begin BusStall = 1'b1; LsuBusRead = 1'b1; - CommittedMfromBus = 1'b1; if(LsuBusAck) begin BusNextState = STATE_BUS_UNCACHED_READ_DONE; end else begin @@ -535,12 +526,10 @@ module lsu end STATE_BUS_UNCACHED_WRITE_DONE: begin - CommittedMfromBus = 1'b1; BusNextState = STATE_BUS_READY; end STATE_BUS_UNCACHED_READ_DONE: begin - CommittedMfromBus = 1'b1; SelUncached = 1'b1; end @@ -548,7 +537,6 @@ module lsu BusStall = 1'b1; PreCntEn = 1'b1; LsuBusRead = 1'b1; - CommittedMfromBus = 1'b1; if (FetchCountFlag & LsuBusAck) begin BusNextState = STATE_BUS_READY; @@ -562,7 +550,6 @@ module lsu BusStall = 1'b1; PreCntEn = 1'b1; LsuBusWrite = 1'b1; - CommittedMfromBus = 1'b1; if(FetchCountFlag & LsuBusAck) begin BusNextState = STATE_BUS_READY; BUSACK = 1'b1; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 0afcddb6..9870f5e8 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -39,7 +39,7 @@ module privileged ( output logic [`XLEN-1:0] PrivilegedNextPCM, output logic RetM, TrapM, output logic ITLBFlushF, DTLBFlushM, - input logic InstrValidM, CommittedM, + input logic InstrValidM, LSUStall, input logic FRegWriteM, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, @@ -230,7 +230,7 @@ module privileged ( .PCM, .InstrMisalignedAdrM, .IEUAdrM, .InstrM, - .InstrValidM, .CommittedM, + .InstrValidM, .LSUStall, .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, .InterruptM, .ExceptionM, diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 02f3f620..bfeb9de2 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -41,7 +41,7 @@ module trap ( input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [31:0] InstrM, - input logic InstrValidM, CommittedM, + input logic InstrValidM, LSUStall, output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic InterruptM, output logic ExceptionM, @@ -61,12 +61,12 @@ module trap ( // Determine pending enabled interrupts // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) - // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice + // & with ~LSUStall to make sure MEPC isn't chosen so as to rerun the same instr twice assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9 assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222)); assign PendingInterruptM = (|PendingIntsM) & InstrValidM; - assign InterruptM = PendingInterruptM & ~CommittedM; + assign InterruptM = PendingInterruptM & ~LSUStall; // previously CommittedM. The purpose is to delay an interrupt if the instruction in the memory stage is busy in the LSU. LSUStall directly provides this. //assign ExceptionM = TrapM; assign ExceptionM = Exception1M; // *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 815799ca..95da6c26 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -125,7 +125,6 @@ module wallypipelinedhart ( (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; logic [`XLEN-1:0] ReadDataW; - logic CommittedM; // AHB ifu interface logic [`PA_BITS-1:0] InstrPAdrF; @@ -240,7 +239,7 @@ module wallypipelinedhart ( // CPU interface .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM, .ExceptionM, .PendingInterruptM, - .CommittedM, .DCacheMiss, .DCacheAccess, + .DCacheMiss, .DCacheAccess, .SquashSCW, //.DataMisalignedM(DataMisalignedM), .IEUAdrE, .IEUAdrM, .WriteDataM, @@ -314,7 +313,7 @@ module wallypipelinedhart ( .InstrM, .CSRReadValW, .PrivilegedNextPCM, .RetM, .TrapM, .ITLBFlushF, .DTLBFlushM, - .InstrValidM, .CommittedM, + .InstrValidM, .LSUStall, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,