From e121dcd4afd314ac9ea07efc2d489ac5cd400267 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Wed, 15 Jun 2022 22:58:33 +0000 Subject: [PATCH] postprocess out of fpu critical path --- pipelined/src/fpu/fsgninj.sv | 29 +++++++++++++++++------------ pipelined/src/fpu/postprocess.sv | 8 +++++--- pipelined/src/fpu/resultsign.sv | 17 +++++++++-------- pipelined/src/fpu/round.sv | 14 +++++++------- 4 files changed, 38 insertions(+), 30 deletions(-) diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index 0a3a3454..0d08d31f 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -56,25 +56,30 @@ module fsgninj ( assign SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]}; else if (`FPSIZES == 2) - assign SgnResE = FmtE ? {ResSgn, FSrcXE[`FLEN-2:0]} : {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]}; + assign SgnResE = {~FmtE|ResSgn, FSrcXE[`FLEN-2:`LEN1], FmtE ? FSrcXE[`LEN1-1] : ResSgn, FSrcXE[`LEN1-2:0]}; - else if (`FPSIZES == 3) + else if (`FPSIZES == 3) begin + logic [2:0] SgnBits; always_comb case (FmtE) - `FMT: SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]}; - `FMT1: SgnResE = {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]}; - `FMT2: SgnResE = {{`FLEN-`LEN2{1'b1}}, ResSgn, FSrcXE[`LEN2-2:0]}; - default: SgnResE = {`FLEN{1'bx}}; + `FMT: SgnBits = {ResSgn, FSrcXE[`LEN1-1], FSrcXE[`LEN2-1]}; + `FMT1: SgnBits = {1'b1, ResSgn, FSrcXE[`LEN2-1]}; + `FMT2: SgnBits = {2'b11, ResSgn}; + default: SgnBits = {3{1'bx}}; endcase + assign SgnResE = {SgnBits[2], FSrcXE[`FLEN-2:`LEN1], SgnBits[1], FSrcXE[`LEN1-2:`LEN2], SgnBits[0], FSrcXE[`LEN2-2:0]}; + - else if (`FPSIZES == 4) + end else if (`FPSIZES == 4) begin + logic [3:0] SgnBits; always_comb case (FmtE) - 2'h3: SgnResE = {ResSgn, FSrcXE[`Q_LEN-2:0]}; - 2'h1: SgnResE = {{`Q_LEN-`D_LEN{1'b1}}, ResSgn, FSrcXE[`D_LEN-2:0]}; - 2'h0: SgnResE = {{`Q_LEN-`S_LEN{1'b1}}, ResSgn, FSrcXE[`S_LEN-2:0]}; - 2'h2: SgnResE = {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, FSrcXE[`H_LEN-2:0]}; + `Q_FMT: SgnBits = {ResSgn, FSrcXE[`D_LEN-1], FSrcXE[`S_LEN-1], FSrcXE[`H_LEN-1]}; + `D_FMT: SgnBits = {1'b1, ResSgn, FSrcXE[`S_LEN-1], FSrcXE[`H_LEN-1]}; + `S_FMT: SgnBits = {2'b11, ResSgn, FSrcXE[`H_LEN-1]}; + `H_FMT: SgnBits = {3'b111, ResSgn}; endcase - + assign SgnResE = {SgnBits[3], FSrcXE[`Q_LEN-2:`D_LEN], SgnBits[2], FSrcXE[`D_LEN-2:`S_LEN], SgnBits[1], FSrcXE[`S_LEN-2:`H_LEN], SgnBits[0], FSrcXE[`H_LEN-2:0]}; + end endmodule diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv index 4cee7147..26764734 100644 --- a/pipelined/src/fpu/postprocess.sv +++ b/pipelined/src/fpu/postprocess.sv @@ -98,6 +98,7 @@ module postprocess( logic DivOp; logic InfIn; logic ResSgn; + logic RoundSgn; logic NaNIn; logic UfLSBRes; logic Sqrt; @@ -171,15 +172,16 @@ module postprocess( // round to nearest max magnitude round round(.OutFmt, .FrmM, .Sticky, .AddendStickyM, .ZZeroM, .Plus1, .PostProcSelM, .CvtCalcExpM, - .InvZM, .ResSgn, .SumExp, .FmaOp, .CvtOp, .CvtResDenormUfM, .CorrShifted, .ToInt, .CvtResUf, + .InvZM, .RoundSgn, .SumExp, .FmaOp, .CvtOp, .CvtResDenormUfM, .CorrShifted, .ToInt, .CvtResUf, .UfPlus1, .FullResExp, .ResFrac, .ResExp, .Round, .RoundAdd, .UfLSBRes, .RoundExp); /////////////////////////////////////////////////////////////////////////////// // Sign calculation /////////////////////////////////////////////////////////////////////////////// - resultsign resultsign(.FrmM, .PSgnM, .PostProcSelM, .ZSgnEffM, .InvZM, .SumExp, .Round, .Sticky, - .ZInfM, .InfIn, .NegSumM, .SumZero, .Mult, .CvtResSgnM, .ResSgn); + resultsign resultsign(.FrmM, .PSgnM, .ZSgnEffM, .InvZM, .SumExp, .Round, .Sticky, + .FmaOp, .DivOp, .CvtOp, .ZInfM, .InfIn, .NegSumM, .SumZero, .Mult, + .CvtResSgnM, .RoundSgn, .ResSgn); /////////////////////////////////////////////////////////////////////////////// // Flags diff --git a/pipelined/src/fpu/resultsign.sv b/pipelined/src/fpu/resultsign.sv index 640e74d6..c8862ff9 100644 --- a/pipelined/src/fpu/resultsign.sv +++ b/pipelined/src/fpu/resultsign.sv @@ -7,13 +7,16 @@ module resultsign( input logic ZInfM, input logic InfIn, input logic NegSumM, - input logic [1:0] PostProcSelM, + input logic FmaOp, + input logic DivOp, + input logic CvtOp, input logic [`NE+1:0] SumExp, input logic SumZero, input logic Mult, input logic Round, input logic Sticky, input logic CvtResSgnM, + output logic RoundSgn, output logic ResSgn ); @@ -40,11 +43,9 @@ module resultsign( assign InfSgn = ZInfM ? ZSgnEffM : PSgnM; assign FmaResSgn = InfIn ? InfSgn : SumZero ? ZeroSgn : FmaResSgnTmp; - always_comb - case(PostProcSelM) - 2'b10: ResSgn = FmaResSgn; // fma - 2'b00: ResSgn = CvtResSgnM; // cvt - 2'b01: ResSgn = 0; // divide - default: ResSgn = 1'bx; - endcase + // Sign for rounding calulation + assign RoundSgn = (FmaResSgnTmp&FmaOp) | (CvtResSgnM&CvtOp) | (1'b0&DivOp); + + assign ResSgn = (FmaResSgn&FmaOp) | (CvtResSgnM&CvtOp) | (1'b0&DivOp); + endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/round.sv b/pipelined/src/fpu/round.sv index ff65d38b..92f1d4c2 100644 --- a/pipelined/src/fpu/round.sv +++ b/pipelined/src/fpu/round.sv @@ -21,7 +21,7 @@ module round( input logic ZZeroM, // is Z zero input logic InvZM, // invert Z input logic [`NE+1:0] SumExp, // exponent of the normalized sum - input logic ResSgn, // the result's sign + input logic RoundSgn, // the result's sign input logic [`NE:0] CvtCalcExpM, // the calculated expoent output logic UfPlus1, // do you add or subtract on from the result output logic [`NE+1:0] FullResExp, // ResExp with bits to determine sign and overflow @@ -230,8 +230,8 @@ module round( case (FrmM) 3'b000: CalcPlus1 = Round & ((Sticky| LSBRes)&~SubBySmallNum);//round to nearest even 3'b001: CalcPlus1 = 0;//round to zero - 3'b010: CalcPlus1 = ResSgn & ~(SubBySmallNum & ~Round);//round down - 3'b011: CalcPlus1 = ~ResSgn & ~(SubBySmallNum & ~Round);//round up + 3'b010: CalcPlus1 = RoundSgn & ~(SubBySmallNum & ~Round);//round down + 3'b011: CalcPlus1 = ~RoundSgn & ~(SubBySmallNum & ~Round);//round up 3'b100: CalcPlus1 = Round & ~SubBySmallNum;//round to nearest max magnitude default: CalcPlus1 = 1'bx; endcase @@ -239,8 +239,8 @@ module round( case (FrmM) 3'b000: UfCalcPlus1 = UfRound & ((UfSticky| UfLSBRes)&~UfSubBySmallNum);//round to nearest even 3'b001: UfCalcPlus1 = 0;//round to zero - 3'b010: UfCalcPlus1 = ResSgn & ~(UfSubBySmallNum & ~UfRound);//round down - 3'b011: UfCalcPlus1 = ~ResSgn & ~(UfSubBySmallNum & ~UfRound);//round up + 3'b010: UfCalcPlus1 = RoundSgn & ~(UfSubBySmallNum & ~UfRound);//round down + 3'b011: UfCalcPlus1 = ~RoundSgn & ~(UfSubBySmallNum & ~UfRound);//round up 3'b100: UfCalcPlus1 = UfRound & ~UfSubBySmallNum;//round to nearest max magnitude default: UfCalcPlus1 = 1'bx; endcase @@ -248,8 +248,8 @@ module round( case (FrmM) 3'b000: CalcMinus1 = 0;//round to nearest even 3'b001: CalcMinus1 = SubBySmallNum & ~Round;//round to zero - 3'b010: CalcMinus1 = ~ResSgn & ~Round & SubBySmallNum;//round down - 3'b011: CalcMinus1 = ResSgn & ~Round & SubBySmallNum;//round up + 3'b010: CalcMinus1 = ~RoundSgn & ~Round & SubBySmallNum;//round down + 3'b011: CalcMinus1 = RoundSgn & ~Round & SubBySmallNum;//round up 3'b100: CalcMinus1 = 0;//round to nearest max magnitude default: CalcMinus1 = 1'bx; endcase