From e0d0fdd70843aae4ac5905fc4c4b6bccb6e38973 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 4 Jun 2021 13:36:06 -0500 Subject: [PATCH] Cleaned up the I-Cache memory. --- wally-pipelined/src/cache/ICacheMem.sv | 127 +++++++++++-------------- 1 file changed, 57 insertions(+), 70 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheMem.sv b/wally-pipelined/src/cache/ICacheMem.sv index d3e876cf..f394b673 100644 --- a/wally-pipelined/src/cache/ICacheMem.sv +++ b/wally-pipelined/src/cache/ICacheMem.sv @@ -1,61 +1,54 @@ `include "wally-config.vh" -module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) ( - // Pipeline stuff - input logic clk, - input logic reset, - // If flush is high, invalidate the entire cache - input logic flush, - - // Select which address to read (broken for efficiency's sake) - input logic [`XLEN-1:0] PCTagF, // physical tag address - input logic [`XLEN-1:0] PCNextIndexF, - // Write new data to the cache - input logic WriteEnable, - input logic [BLOCKLEN-1:0] WriteLine, - // Output the word, as well as if it is valid - output logic [31:0] DataWord, // *** was `XLEN-1 - output logic DataValid -); +module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) + ( + // Pipeline stuff + input logic clk, + input logic reset, + // If flush is high, invalidate the entire cache + input logic flush, - // Various compile-time constants - localparam integer WORDWIDTH = $clog2(`XLEN/8); - localparam integer OFFSETWIDTH = $clog2(BLOCKLEN/`XLEN); - localparam integer SETWIDTH = $clog2(NUMLINES); - localparam integer TAGWIDTH = `XLEN - OFFSETWIDTH - SETWIDTH - WORDWIDTH; + // Select which address to read (broken for efficiency's sake) + input logic [`XLEN-1:0] PCTagF, // physical tag address + input logic [`XLEN-1:0] PCNextIndexF, + // Write new data to the cache + input logic WriteEnable, + input logic [BLOCKLEN-1:0] WriteLine, + // Output the word, as well as if it is valid + output logic [31:0] DataWord, // *** was `XLEN-1 + output logic DataValid + ); - localparam integer OFFSETBEGIN = WORDWIDTH; - localparam integer OFFSETEND = OFFSETBEGIN+OFFSETWIDTH-1; - localparam integer SETBEGIN = OFFSETEND+1; - localparam integer SETEND = SETBEGIN + SETWIDTH - 1; - localparam integer TAGBEGIN = SETEND + 1; - localparam integer TAGEND = TAGBEGIN + TAGWIDTH - 1; + // divide the address bus into sections, tag, index, offset + localparam BLOCKBYTELEN = BLOCKLEN/8; + localparam OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam INDEXLEN = $clog2(NUMLINES); + localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN; - // Machinery to read from and write to the correct addresses in memory - logic [BLOCKLEN-1:0] ReadLine; - logic [BLOCKLEN/`XLEN-1:0][`XLEN-1:0] ReadLineTransformed; + // Machinery to read from and write to the correct addresses in memory + logic [BLOCKLEN-1:0] ReadLine; - // Machinery to check if a given read is valid and is the desired value - logic [TAGWIDTH-1:0] DataTag; - logic [NUMLINES-1:0] ValidOut; - logic DataValidBit; + // Machinery to check if a given read is valid and is the desired value + logic [TAGLEN-1:0] DataTag; + logic [NUMLINES-1:0] ValidOut; + logic DataValidBit; - // Depth is number of bits in one "word" of the memory, width is number of such words - sram1rw #(.DEPTH(BLOCKLEN), .WIDTH(NUMLINES)) cachemem ( - .*, - .Addr(PCNextIndexF[SETEND:SETBEGIN]), - .ReadData(ReadLine), - .WriteData(WriteLine) - ); - sram1rw #(.DEPTH(TAGWIDTH), .WIDTH(NUMLINES)) cachetags ( - .*, - .Addr(PCNextIndexF[SETEND:SETBEGIN]), - .ReadData(DataTag), - .WriteData(PCTagF[TAGEND:TAGBEGIN]) - ); + // Depth is number of bits in one "word" of the memory, width is number of such words + sram1rw #(.DEPTH(BLOCKLEN), .WIDTH(NUMLINES)) + cachemem (.*, + .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .ReadData(ReadLine), + .WriteData(WriteLine) + ); + sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES)) + cachetags (.*, + .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .ReadData(DataTag), + .WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]) + ); - // Pick the right bits coming out the read line - //assign DataWord = ReadLineTransformed[ReadOffset]; + // Pick the right bits coming out the read line + //assign DataWord = ReadLineTransformed[ReadOffset]; //logic [31:0] tempRD; always_comb begin case (PCTagF[4:1]) @@ -80,25 +73,19 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) ( 15: DataWord = {16'b0, ReadLine[255:240]}; endcase end - genvar i; - generate - for (i=0; i < BLOCKLEN/`XLEN; i++) begin - assign ReadLineTransformed[i] = ReadLine[(i+1)*`XLEN-1:i*`XLEN]; - end - endgenerate - // Correctly handle the valid bits - always_ff @(posedge clk, posedge reset) begin - if (reset) begin - ValidOut <= {NUMLINES{1'b0}}; - end else if (flush) begin - ValidOut <= {NUMLINES{1'b0}}; - end else begin - if (WriteEnable) begin - ValidOut[PCNextIndexF[SETEND:SETBEGIN]] <= 1; - end - end - DataValidBit <= ValidOut[PCNextIndexF[SETEND:SETBEGIN]]; - end - assign DataValid = DataValidBit && (DataTag == PCTagF[TAGEND:TAGBEGIN]); + // Correctly handle the valid bits + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + ValidOut <= {NUMLINES{1'b0}}; + end else if (flush) begin + ValidOut <= {NUMLINES{1'b0}}; + end else begin + if (WriteEnable) begin + ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= 1; + end + end + DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]]; + end + assign DataValid = DataValidBit && (DataTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]); endmodule