From e0c310fea7d778151fe59e5bd6918837ba9be378 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 3 Jan 2022 13:27:15 -0600
Subject: [PATCH] Fixed a bug where the instruction fetch got out of sync with
 the icache.

---
 wally-pipelined/src/cache/icachefsm.sv | 3 +++
 wally-pipelined/src/ifu/ifu.sv         | 3 ++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index eb754377..cfbff379 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -128,6 +128,9 @@ module icachefsm
       STATE_READY: begin
         SelAdr = 2'b00;
         ICacheReadEn = 1'b1;
+		if(IgnoreRequest) begin
+		  NextState = STATE_READY;
+		end else 
 		if(ITLBMissF) begin
 		  NextState = STATE_READY;
 		  SelAdr = 2'b01;
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 31ca6d16..242f57fc 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -244,7 +244,8 @@ module ifu (
 
   assign IfuStallF = ICacheStallF | BusStall;
 
-  assign IgnoreRequest = ITLBMissF | ExceptionM | PendingInterruptM;
+  //assign IgnoreRequest = ITLBMissF | ExceptionM | PendingInterruptM;
+  assign IgnoreRequest = ITLBMissF;