From dfddca3ed3702854bd66fb96cf73f01023991d7c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 7 Jan 2023 04:49:38 -0800
Subject: [PATCH] Started vclean script to clean Verilog

---
 bin/vclean.pl | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 bin/vclean.pl

diff --git a/bin/vclean.pl b/bin/vclean.pl
new file mode 100644
index 00000000..73f1381f
--- /dev/null
+++ b/bin/vclean.pl
@@ -0,0 +1,11 @@
+#!/usr/bin/perl -w
+
+# vclean.pl
+# David_Harris@hmc.edu 7 December 2023
+# Identifies unused signals in Verilog files
+#   verilator should do this, but it also reports partially used signals
+
+for (my $i=0; $i<=$#ARGV; $i++) {
+    my $fname = $ARGV[$i];
+    printf ("$fname\n");
+}