From 33358d101ed17885cb5c4fa83f61f47e3f667595 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 10:12:33 -0700 Subject: [PATCH 01/10] Lint cleanup: ahblite, ifu, hart --- wally-pipelined/src/ebu/ahblite.sv | 7 +------ wally-pipelined/src/ifu/ifu.sv | 6 ++---- .../src/wally/wallypipelinedhart.sv | 20 ++++--------------- 3 files changed, 7 insertions(+), 26 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 5bad2e7b..13a095c4 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -36,11 +36,9 @@ endpackage module ahblite ( input logic clk, reset, - input logic StallW, // Load control input logic UnsignedLoadM, input logic [1:0] AtomicMaskedM, - input logic [6:0] Funct7M, // Signals from Instruction Cache input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram input logic InstrReadF, @@ -75,14 +73,11 @@ module ahblite ( logic GrantData; logic [31:0] AccessAddress; logic [2:0] ISize; - logic [`AHBW-1:0] HRDATAMasked, ReadDataM, HRDATANext, CapturedHRDATAMasked, WriteData; - logic IReady, DReady; - logic CaptureDataM,CapturedDataAvailable; assign HCLK = clk; assign HRESETn = ~reset; - // *** initially support AHBW = XLEN + // initially support AHBW = XLEN // track bus state // Data accesses have priority over instructions. However, if a data access comes diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 69f61d8e..c3eabf26 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -76,15 +76,13 @@ module ifu ( input logic ITLBWriteF, ITLBFlushF, input logic WalkerInstrPageFaultF, - output logic ITLBMissF, ITLBHitF, + output logic ITLBMissF, // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], - output logic InstrAccessFaultF, - - output logic ISquashBusAccessF + output logic InstrAccessFaultF ); logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 8a298594..985d8c5c 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -94,8 +94,7 @@ module wallypipelinedhart logic SquashSCM, SquashSCW; // floating point unit signals logic [2:0] FRM_REGW; - logic [1:0] FMemRWM, FMemRWE; - logic [4:0] RdE, RdM, RdW; + logic [4:0] RdE, RdM, RdW; logic FStallD; logic FWriteIntE, FWriteIntM, FWriteIntW; logic [`XLEN-1:0] FWriteDataE; @@ -108,10 +107,10 @@ module wallypipelinedhart logic [`XLEN-1:0] FPUResultW; // memory management unit signals - logic ITLBWriteF, DTLBWriteM; + logic ITLBWriteF; logic ITLBFlushF, DTLBFlushM; - logic ITLBMissF, ITLBHitF; - logic DTLBMissM, DTLBHitM; + logic ITLBMissF; + logic DTLBHitM; logic [`XLEN-1:0] SATP_REGW; logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; logic [1:0] STATUS_MPP; @@ -120,7 +119,6 @@ module wallypipelinedhart logic [1:0] PageType; // PMA checker signals - logic DSquashBusAccessM, ISquashBusAccessF; var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; @@ -233,9 +231,6 @@ module wallypipelinedhart .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerStorePageFaultM(WalkerStorePageFaultM), - - .DTLBHitM(DTLBHitM), // not connected remove - .LSUStall(LSUStall)); // change to LSUStall @@ -256,9 +251,6 @@ module wallypipelinedhart // remove these .MemSizeM(DCtoAHBSizeM[1:0]), // *** depends on XLEN should be removed .UnsignedLoadM(1'b0), - .Funct7M(7'b0), -// .HRDATAW(), - .StallW(1'b0), .AtomicMaskedM(2'b00), .*); @@ -272,9 +264,5 @@ module wallypipelinedhart fpu fpu(.*); // floating point unit - // add FPU here, with SetFflagsM, FRM_REGW - // presently stub out SetFlagsM and FRegWriteM - //assign SetFflagsM = 0; - //assign FRegWriteM = 0; endmodule From 8e516e639132b6fa39ec109c5ed4e8a361aeea83 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 10:29:52 -0700 Subject: [PATCH 02/10] Lint cleanup from wallypipeliendhart --- wally-pipelined/src/ieu/ieu.sv | 4 ++-- wally-pipelined/src/ifu/ifu.sv | 1 + wally-pipelined/src/lsu/lsu.sv | 3 +-- wally-pipelined/src/muldiv/muldiv.sv | 4 +--- wally-pipelined/src/privileged/privileged.sv | 4 ++-- wally-pipelined/src/wally/wallypipelinedhart.sv | 10 ++-------- wally-pipelined/src/wally/wallypipelinedsoc.sv | 6 ++---- 7 files changed, 11 insertions(+), 21 deletions(-) diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 234f767a..b6146650 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -31,7 +31,6 @@ module ieu ( input logic [31:0] InstrD, input logic IllegalIEUInstrFaultD, output logic IllegalBaseInstrFaultD, - output logic RegWriteD, // Execute Stage interface input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCLinkE, @@ -48,7 +47,6 @@ module ieu ( // Memory stage interface input logic DataMisalignedM, // from LSU input logic SquashSCW, // from LSU - output logic [1:0] MemRWE, // read/write control goes to LSU output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] AtomicE, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU @@ -87,6 +85,8 @@ module ieu ( logic TargetSrcE; logic SCE; logic InstrValidW; + logic [1:0] MemRWE; + logic RegWriteD; // forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index c3eabf26..aa53e6ac 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -100,6 +100,7 @@ module ifu ( logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. logic [`XLEN+1:0] PCFExt; + logic ITLBHitF, ISquashBusAccessF; generate if (`XLEN==32) begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index feb212e8..304733e8 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -89,14 +89,13 @@ module lsu output logic WalkerLoadPageFaultM, output logic WalkerStorePageFaultM, - output logic DTLBHitM, // not connected - input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. ); logic SquashSCM; logic DTLBPageFaultM; + logic DTLBHitM; logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv index 4bad2d30..a98fb4f0 100644 --- a/wally-pipelined/src/muldiv/muldiv.sv +++ b/wally-pipelined/src/muldiv/muldiv.sv @@ -27,8 +27,6 @@ module muldiv ( input logic clk, reset, - // Decode Stage interface - input logic [31:0] InstrD, // Execute Stage interface input logic [`XLEN-1:0] SrcAE, SrcBE, input logic [2:0] Funct3E, Funct3M, @@ -38,7 +36,7 @@ module muldiv ( // Divide Done output logic DivBusyE, // hazards - input logic StallE, StallM, StallW, FlushM, FlushW + input logic StallM, StallW, FlushM, FlushW ); generate diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 326ebcaa..a6c3f2d8 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -32,8 +32,8 @@ module privileged ( input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW, input logic CSRReadM, CSRWriteM, input logic [`XLEN-1:0] SrcAM, - input logic [`XLEN-1:0] PCF,PCD,PCE,PCM, - input logic [31:0] InstrD, InstrE, InstrM, InstrW, + input logic [`XLEN-1:0] PCM, + input logic [31:0] InstrM, output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] PrivilegedNextPCM, output logic RetM, TrapM, diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 985d8c5c..398b37db 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -36,7 +36,6 @@ module wallypipelinedhart input logic DataAccessFaultM, input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, // Bus Interface - input logic [15:0] rd2, // bogus, delete when real multicycle fetch works input logic [`AHBW-1:0] HRDATA, input logic HREADY, HRESP, output logic HCLK, HRESETn, @@ -48,7 +47,6 @@ module wallypipelinedhart output logic [3:0] HPROT, output logic [1:0] HTRANS, output logic HMASTLOCK, - output logic [5:0] HSELRegions, // Delayed signals for subword write output logic [2:0] HADDRD, output logic [3:0] HSIZED, @@ -70,11 +68,10 @@ module wallypipelinedhart logic [2:0] Funct3E; // logic [31:0] InstrF; logic [31:0] InstrD, InstrE, InstrM, InstrW; - logic [`XLEN-1:0] PCD, PCE, PCM, PCLinkE, PCLinkW; + logic [`XLEN-1:0] PCD, PCE, PCM, PCLinkE; logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; - logic [1:0] MemRWE; logic [1:0] MemRWM; logic InstrValidM; logic InstrMisalignedFaultM; @@ -89,9 +86,8 @@ module wallypipelinedhart logic PCSrcE; logic CSRWritePendingDEM; logic DivBusyE; - logic RegWriteD; logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD; - logic SquashSCM, SquashSCW; + logic SquashSCW; // floating point unit signals logic [2:0] FRM_REGW; logic [4:0] RdE, RdM, RdW; @@ -104,13 +100,11 @@ module wallypipelinedhart logic FRegWriteM; logic FPUStallD; logic [4:0] SetFflagsM; - logic [`XLEN-1:0] FPUResultW; // memory management unit signals logic ITLBWriteF; logic ITLBFlushF, DTLBFlushM; logic ITLBMissF; - logic DTLBHitM; logic [`XLEN-1:0] SATP_REGW; logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; logic [1:0] STATUS_MPP; diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 9ac700bd..fa93bdf0 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -60,7 +60,6 @@ module wallypipelinedsoc ( // Uncore signals logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore logic HREADY, HRESP; - logic [5:0] HSELRegions; logic InstrAccessFaultF, DataAccessFaultM; logic TimerIntM, SwIntM; // from CLINT logic [63:0] MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs @@ -68,16 +67,15 @@ module wallypipelinedsoc ( logic [2:0] HADDRD; logic [3:0] HSIZED; logic HWRITED; - logic [15:0] rd2; // bogus, delete when real multicycle fetch works logic [31:0] InstrF; // instantiate processor and memories wallypipelinedhart hart(.clk, .reset, .PCF, .TimerIntM, .ExtIntM, .SwIntM, .DataAccessFaultM, - .MTIME_CLINT, .MTIMECMP_CLINT, .rd2, + .MTIME_CLINT, .MTIMECMP_CLINT, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, - .HSELRegions, .HADDRD, .HSIZED, .HWRITED + .HADDRD, .HSIZED, .HWRITED ); // instructions now come from uncore memory. This line can be removed at any time. From d570df864f2834068aedcb62dcb0a246da667da3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 10:51:53 -0700 Subject: [PATCH 03/10] IEU lint cleanup --- wally-pipelined/src/ieu/controller.sv | 14 ++++++-------- wally-pipelined/src/ieu/ieu.sv | 2 -- wally-pipelined/src/uncore/uncore.sv | 6 +----- wally-pipelined/src/wally/wallypipelinedsoc.sv | 9 +-------- 4 files changed, 8 insertions(+), 23 deletions(-) diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index ed5f0240..38f7869a 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -34,9 +34,8 @@ module controller( output logic [2:0] ImmSrcD, input logic IllegalIEUInstrFaultD, output logic IllegalBaseInstrFaultD, - output logic RegWriteD, // Execute stage control signals - input logic StallE, FlushE, + input logic StallE, FlushE, input logic [2:0] FlagsE, output logic PCSrcE, // for datapath and Hazard Unit output logic [4:0] ALUControlE, @@ -46,7 +45,6 @@ module controller( output logic [2:0] Funct3E, output logic MulDivE, W64E, output logic JumpE, - output logic [1:0] MemRWE, // Memory stage control signals input logic StallM, FlushM, output logic [1:0] MemRWM, @@ -57,7 +55,7 @@ module controller( output logic [2:0] Funct3M, output logic RegWriteM, // for Hazard Unit output logic InvalidateICacheM, FlushDCacheM, - output logic InstrValidM, InstrValidW, + output logic InstrValidM, // Writeback stage control signals input logic StallW, FlushW, output logic RegWriteW, // for datapath and Hazard Unit @@ -75,9 +73,9 @@ module controller( `define CTRLW 24 // pipelined control signals - logic RegWriteE; + logic RegWriteD, RegWriteE; logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; - logic [1:0] MemRWD; + logic [1:0] MemRWD, MemRWE; logic JumpD; logic BranchD, BranchE; logic [1:0] ALUOpD; @@ -233,8 +231,8 @@ module controller( // Writeback stage pipeline control register flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW, - {RegWriteM, ResultSrcM, InstrValidM}, - {RegWriteW, ResultSrcW, InstrValidW}); + {RegWriteM, ResultSrcM}, + {RegWriteW, ResultSrcW}); assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM; diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index b6146650..934a440d 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -85,8 +85,6 @@ module ieu ( logic TargetSrcE; logic SCE; logic InstrValidW; - logic [1:0] MemRWE; - logic RegWriteD; // forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index 78a89b02..943572f1 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -47,9 +47,6 @@ module uncore ( input logic [2:0] HADDRD, input logic [3:0] HSIZED, input logic HWRITED, - // bus interface - // PMA checker now handles access faults. *** This can be deleted - // output logic DataAccessFaultM, // peripheral pins output logic TimerIntM, SwIntM, ExtIntM, input logic [31:0] GPIOPinsIn, @@ -63,14 +60,13 @@ module uncore ( logic [`XLEN-1:0] HREADTim, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART; logic [6:0] HSELRegions; - logic HSELTim, HSELCLINT, HSELPLIC, HSELGPIO, PreHSELUART, HSELUART; + logic HSELTim, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART; logic HSELTimD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD; logic HRESPTim, HRESPCLINT, HRESPPLIC, HRESPGPIO, HRESPUART; logic HREADYTim, HREADYCLINT, HREADYPLIC, HREADYGPIO, HREADYUART; logic [`XLEN-1:0] HREADBootTim; logic HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim; logic HSELNoneD; - logic [1:0] MemRWboottim; logic UARTIntr,GPIOIntr; // Determine which region of physical memory (if any) is being accessed diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index fa93bdf0..94588958 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -54,32 +54,25 @@ module wallypipelinedsoc ( output logic UARTSout ); - // to instruction memory *** remove later - logic [`XLEN-1:0] PCF; - // Uncore signals logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore logic HREADY, HRESP; - logic InstrAccessFaultF, DataAccessFaultM; logic TimerIntM, SwIntM; // from CLINT logic [63:0] MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs logic ExtIntM; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; logic HWRITED; - logic [31:0] InstrF; // instantiate processor and memories wallypipelinedhart hart(.clk, .reset, - .PCF, .TimerIntM, .ExtIntM, .SwIntM, .DataAccessFaultM, + .TimerIntM, .ExtIntM, .SwIntM, .MTIME_CLINT, .MTIMECMP_CLINT, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HWRITED ); - // instructions now come from uncore memory. This line can be removed at any time. - // imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished*** uncore uncore(.HCLK, .HRESETn, .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, From 4bf823e06397884d378e9050b75dc384a906691b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 11:03:28 -0700 Subject: [PATCH 04/10] lint cleanup --- wally-pipelined/src/ieu/controller.sv | 2 +- wally-pipelined/src/ieu/ieu.sv | 2 -- wally-pipelined/src/wally/wallypipelinedhart.sv | 8 ++------ 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 38f7869a..449066bf 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -230,7 +230,7 @@ module controller( {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, AtomicM, InvalidateICacheM, FlushDCacheM, InstrValidM}); // Writeback stage pipeline control register - flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW, + flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW, {RegWriteM, ResultSrcM}, {RegWriteW, ResultSrcW}); diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 934a440d..4641f6c0 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -55,7 +55,6 @@ module ieu ( output logic [2:0] Funct3M, // size and signedness to LSU output logic [`XLEN-1:0] SrcAM, // to privilege and fpu output logic [4:0] RdM, - input logic DataAccessFaultM, input logic [`XLEN-1:0] FIntResM, output logic InvalidateICacheM, FlushDCacheM, @@ -84,7 +83,6 @@ module ieu ( logic [2:0] ResultSrcW; logic TargetSrcE; logic SCE; - logic InstrValidW; // forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 398b37db..1a4c826e 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -26,14 +26,10 @@ `include "wally-config.vh" /* verilator lint_on UNUSED */ -module wallypipelinedhart - ( +module wallypipelinedhart ( input logic clk, reset, - output logic [`XLEN-1:0] PCF, - // input logic [31:0] InstrF, // Privileged input logic TimerIntM, ExtIntM, SwIntM, - input logic DataAccessFaultM, input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, // Bus Interface input logic [`AHBW-1:0] HRDATA, @@ -68,7 +64,7 @@ module wallypipelinedhart logic [2:0] Funct3E; // logic [31:0] InstrF; logic [31:0] InstrD, InstrE, InstrM, InstrW; - logic [`XLEN-1:0] PCD, PCE, PCM, PCLinkE; + logic [`XLEN-1:0] PCF, PCD, PCE, PCM, PCLinkE; logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; From 8d9efcbafbf6b4b79e1aeeffaf888b654635fa3c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 11:13:28 -0700 Subject: [PATCH 05/10] IEU cleanup --- wally-pipelined/src/fpu/fpu.sv | 38 +++++++++---------- wally-pipelined/src/hazard/hazard.sv | 2 - wally-pipelined/src/ieu/ieu.sv | 2 - wally-pipelined/src/mmu/priorityonehot.sv | 2 +- .../src/mmu/prioritythermometer.sv | 2 +- 5 files changed, 19 insertions(+), 27 deletions(-) diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index 810eac6f..6ce894be 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -31,10 +31,9 @@ module fpu ( input logic [31:0] InstrD, // instruction from IFU input logic [`XLEN-1:0] ReadDataW,// Read data from memory input logic [`XLEN-1:0] SrcAE, // Integer input being processed (from IEU) - input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg (from IEU) input logic StallE, StallM, StallW, // stall signals from HZU input logic FlushE, FlushM, FlushW, // flush signals from HZU - input logic [4:0] RdE, RdM, RdW, // which FP register to write to (from IEU) + input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) output logic FRegWriteM, // FP register write enable output logic FStallD, // Stall the decode stage output logic FWriteIntE, FWriteIntM, FWriteIntW, // integer register write enable @@ -68,8 +67,8 @@ module fpu ( logic [1:0] FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals logic [1:0] FResultSelD, FResultSelE; // Select the result written to FP register logic [1:0] FResultSelM, FResultSelW; // Select the result written to FP register - logic [2:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component - logic [2:0] FResSelD, FResSelE, FResSelM; // Select one of the results that finish in the memory stage + logic [2:0] FOpCtrlD, FOpCtrlE; // Select which opperation to do in each component + logic [2:0] FResSelD, FResSelE; // Select one of the results that finish in the memory stage logic [1:0] FIntResSelD, FIntResSelE; // Select the result written to the integer resister logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input @@ -103,24 +102,23 @@ module fpu ( logic XExpMaxE; // is the exponent all ones (max value) logic XNormE; // is normal logic FmtQ; - logic FDivStartQ; logic FOpCtrlQ; // result and flag signals logic [63:0] FDivResM, FDivResW; // divide/squareroot result - logic [4:0] FDivFlgM, FDivFlgW; // divide/squareroot flags + logic [4:0] FDivFlgM; // divide/squareroot flags logic [63:0] FMAResM, FMAResW; // FMA/multiply result - logic [4:0] FMAFlgM, FMAFlgW; // FMA/multiply result + logic [4:0] FMAFlgM; // FMA/multiply result logic [63:0] ReadResW; // read result (load instruction) - logic [63:0] CvtFpResE, CvtFpResM, CvtFpResW; // add/FP -> FP convert result - logic [4:0] CvtFpFlgE, CvtFpFlgM, CvtFpFlgW; // add/FP -> FP convert flags - logic [63:0] CvtResE, CvtResM; // FP <-> int convert result - logic [4:0] CvtFlgE, CvtFlgM; // FP <-> int convert flags //*** trim this - logic [63:0] ClassResE, ClassResM; // classify result - logic [63:0] CmpResE, CmpResM; // compare result - logic CmpNVE, CmpNVM; // compare invalid flag (Not Valid) - logic [63:0] SgnResE, SgnResM; // sign injection result - logic SgnNVE, SgnNVM; // sign injection invalid flag (Not Valid) + logic [63:0] CvtFpResE; // add/FP -> FP convert result + logic [4:0] CvtFpFlgE; // add/FP -> FP convert flags + logic [63:0] CvtResE; // FP <-> int convert result + logic [4:0] CvtFlgE; // FP <-> int convert flags //*** trim this + logic [63:0] ClassResE; // classify result + logic [63:0] CmpResE; // compare result + logic CmpNVE; // compare invalid flag (Not Valid) + logic [63:0] SgnResE; // sign injection result + logic SgnNVE; // sign injection invalid flag (Not Valid) logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage logic [`XLEN-1:0] FIntResE; @@ -128,7 +126,6 @@ module fpu ( // other signals logic FDivSqrtDoneE; // is divide done logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit - logic FDivClk; // clock for divide/squareroot unit logic load_preload; // enable for FF on fpdivsqrt logic [63:0] AlignedSrcAE; // align SrcA to the floating point format @@ -263,9 +260,9 @@ module fpu ( flopenrc #(64) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM); flopenrc #(5) EMRegCmpFlg (clk, reset, FlushM, ~StallM, FFlgE, FFlgM); flopenrc #(`XLEN) EMRegSgnRes (clk, reset, FlushM, ~StallM, FIntResE, FIntResM); - flopenrc #(11) EMCtrlReg (clk, reset, FlushM, ~StallM, - {FRegWriteE, FResultSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE}, - {FRegWriteM, FResultSelM, FrmM, FmtM, FOpCtrlM, FWriteIntM}); + flopenrc #(8) EMCtrlReg (clk, reset, FlushM, ~StallM, + {FRegWriteE, FResultSelE, FrmE, FmtE, FWriteIntE}, + {FRegWriteM, FResultSelM, FrmM, FmtM, FWriteIntM}); // BEGIN MEMORY STAGE @@ -275,7 +272,6 @@ module fpu ( // M/W pipe registers flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); - flopenrc #(64) MWRegAdd(clk, reset, FlushW, ~StallW, CvtFpResM, CvtFpResW); flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW); flopenrc #(5) MWCtrlReg(clk, reset, FlushW, ~StallW, {FRegWriteM, FResultSelM, FmtM, FWriteIntM}, diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 0a16a8fd..72deeac0 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -26,8 +26,6 @@ `include "wally-config.vh" module hazard( - input logic clk, - input logic reset, // Detect hazards input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD, diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 4641f6c0..b469df63 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -45,7 +45,6 @@ module ieu ( input logic FWriteIntM, // Memory stage interface - input logic DataMisalignedM, // from LSU input logic SquashSCW, // from LSU output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] AtomicE, // atomic control goes to LSU @@ -70,7 +69,6 @@ module ieu ( input logic FlushD, FlushE, FlushM, FlushW, output logic FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD, output logic PCSrcE, - input logic DivBusyE, output logic CSRReadM, CSRWriteM, PrivilegedM, output logic CSRWritePendingDEM, output logic StoreStallD diff --git a/wally-pipelined/src/mmu/priorityonehot.sv b/wally-pipelined/src/mmu/priorityonehot.sv index f02f8ccc..849f178e 100644 --- a/wally-pipelined/src/mmu/priorityonehot.sv +++ b/wally-pipelined/src/mmu/priorityonehot.sv @@ -40,7 +40,7 @@ module priorityonehot #(parameter ENTRIES = 8) ( logic [ENTRIES-1:0] nolower; // generate thermometer code mask - prioritythemometer #(ENTRIES) maskgen(.a({a[ENTRIES-2:0], 1'b1}), .y(nolower)); + prioritythermometer #(ENTRIES) maskgen(.a({a[ENTRIES-2:0], 1'b1}), .y(nolower)); // genvar i; // generate // assign nolower[0] = 1'b1; diff --git a/wally-pipelined/src/mmu/prioritythermometer.sv b/wally-pipelined/src/mmu/prioritythermometer.sv index a3eab7e4..8ff099a0 100644 --- a/wally-pipelined/src/mmu/prioritythermometer.sv +++ b/wally-pipelined/src/mmu/prioritythermometer.sv @@ -32,7 +32,7 @@ /* verilator lint_off UNOPTFLAT */ -module prioritythemometer #(parameter N = 8) ( +module prioritythermometer #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y ); From 61fdb3d902c1a4249b122aadb8b90a1e6dd251ec Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 11:24:36 -0700 Subject: [PATCH 06/10] random lint cleanup --- wally-pipelined/src/fpu/fma.sv | 8 ++++---- wally-pipelined/src/ieu/ieu.sv | 2 +- wally-pipelined/src/mmu/tlb.sv | 1 - wally-pipelined/src/privileged/csrc.sv | 4 ++-- wally-pipelined/src/uncore/clint.sv | 3 +-- wally-pipelined/src/uncore/dtim.sv | 1 - 6 files changed, 8 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv index c4a115a0..db55ee5c 100644 --- a/wally-pipelined/src/fpu/fma.sv +++ b/wally-pipelined/src/fpu/fma.sv @@ -468,9 +468,8 @@ module fma2( logic Plus1, Minus1, CalcPlus1; // do you add or subtract one for rounding logic UfPlus1; // do you add one (for determining underflow flag) logic Invalid,Underflow,Overflow; // flags - logic ResultSgnTmp; // the result's sign assuming the result is not zero logic Guard, Round; // bits needed to determine rounding - logic UfRound, UfLSBNormSum; // bits needed to determine rounding for underflow flag + logic UfLSBNormSum; // bits needed to determine rounding for underflow flag @@ -497,7 +496,7 @@ module fma2( // round to nearest max magnitude fmaround fmaround(.FmtM, .FrmM, .Sticky, .UfSticky, .NormSum, .AddendStickyM, .NormSumSticky, .ZZeroM, .InvZM, .ResultSgn, .SumExp, - .CalcPlus1, .Plus1, .UfPlus1, .Minus1, .FullResultExp, .ResultFrac, .ResultExp, .Round, .Guard, .UfRound, .UfLSBNormSum); + .CalcPlus1, .Plus1, .UfPlus1, .Minus1, .FullResultExp, .ResultFrac, .ResultExp, .Round, .Guard, .UfLSBNormSum); @@ -688,7 +687,7 @@ module fmaround( output logic [`NF-1:0] ResultFrac, // Result fraction output logic [`NE-1:0] ResultExp, // Result exponent output logic Sticky, // sticky bit - output logic Round, Guard, UfRound, UfLSBNormSum // bits needed to calculate rounding + output logic Round, Guard, UfLSBNormSum // bits needed to calculate rounding ); logic LSBNormSum; // bit used for rounding - least significant bit of the normalized sum logic SubBySmallNum, UfSubBySmallNum; // was there supposed to be a subtraction by a small number @@ -696,6 +695,7 @@ module fmaround( logic UfCalcPlus1, CalcMinus1; // do you add or subtract on from the result logic [`FLEN:0] RoundAdd; // how much to add to the result logic [`NF-1:0] NormSumTruncated; // the normalized sum trimed to fit the mantissa + logic UfRound; /////////////////////////////////////////////////////////////////////////////// // Rounding diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index b469df63..d3babff3 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -41,7 +41,6 @@ module ieu ( output logic MulDivE, W64E, output logic [2:0] Funct3E, output logic [`XLEN-1:0] SrcAE, SrcBE, - output logic [4:0] RdE, input logic FWriteIntM, // Memory stage interface @@ -81,6 +80,7 @@ module ieu ( logic [2:0] ResultSrcW; logic TargetSrcE; logic SCE; + logic [4:0] RdE; // forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index f4902ed3..d3b8e6de 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -98,7 +98,6 @@ module tlb #(parameter TLB_ENTRIES = 8, // Sections of the page table entry logic [7:0] PTEAccessBits; - logic [11:0] PageOffset; logic [1:0] HitPageType; logic CAMHit; diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index 35dc6f65..647f859b 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -71,8 +71,8 @@ module csrc #(parameter //HPMCOUNTER31H = 12'hC9F ) ( input logic clk, reset, - input logic StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, + input logic StallE, StallM, StallW, + input logic FlushE, FlushM, FlushW, input logic InstrValidM, LoadStallD, CSRMWriteM, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index 817096d3..362d11ae 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -42,11 +42,10 @@ module clint ( logic MSIP; logic [15:0] entry, entryd; - logic memread, memwrite; + logic memwrite; logic initTrans; assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00); - assign memread = initTrans & ~HWRITE; // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite); flopr #(16) entrydflop(HCLK, ~HRESETn, entry, entryd); diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index a331055c..3a0b16be 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -46,7 +46,6 @@ module dtim #(parameter BASE=0, RANGE = 65535) ( logic prevHREADYTim, risingHREADYTim; logic initTrans; - logic [15:0] entry; logic memwrite; logic [3:0] busycount; From 62a23fe878fa0c5bd0e7fa1d4d3d6f6c89274363 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 11:41:20 -0700 Subject: [PATCH 07/10] lsu/ifu lint cleanup --- wally-pipelined/src/ifu/ifu.sv | 4 +--- wally-pipelined/src/lsu/lrsc.sv | 3 +-- wally-pipelined/src/lsu/lsu.sv | 7 +++---- wally-pipelined/src/mmu/mmu.sv | 10 +++------- wally-pipelined/src/privileged/csr.sv | 4 ++-- 5 files changed, 10 insertions(+), 18 deletions(-) diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index aa53e6ac..7a23800b 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -100,7 +100,7 @@ module ifu ( logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. logic [`XLEN+1:0] PCFExt; - logic ITLBHitF, ISquashBusAccessF; + logic ITLBHitF; generate if (`XLEN==32) begin @@ -123,13 +123,11 @@ module ifu ( .TLBFlush(ITLBFlushF), .PhysicalAddress(PCPFmmu), .TLBMiss(ITLBMissF), - .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), .ExecuteAccessF(1'b1), // ***dh -- this should eventually change to only true if an instruction fetch is occurring .AtomicAccessM(1'b0), .ReadAccessM(1'b0), .WriteAccessM(1'b0), - .SquashBusAccess(ISquashBusAccessF), .LoadAccessFaultM(), .StoreAccessFaultM(), .DisableTranslation(1'b0), diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv index cadf58bb..64bdbdd4 100644 --- a/wally-pipelined/src/lsu/lrsc.sv +++ b/wally-pipelined/src/lsu/lrsc.sv @@ -35,7 +35,6 @@ module lrsc output logic [1:0] MemRWMtoDCache, input logic [1:0] AtomicMtoDCache, input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache - output logic SquashSCM, output logic SquashSCW ); // Handle atomic load reserved / store conditional @@ -44,6 +43,7 @@ module lrsc logic [`PA_BITS-1:2] ReservationPAdrW; logic ReservationValidM, ReservationValidW; logic lrM, scM, WriteAdrMatchM; + logic SquashSCM; assign lrM = MemReadM && AtomicMtoDCache[0]; assign scM = MemRWMtoLRSC[0] && AtomicMtoDCache[0]; @@ -59,7 +59,6 @@ module lrsc flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCW); end else begin // Atomic operations not supported - assign SquashSCM = 0; assign SquashSCW = 0; assign MemRWMtoDCache = MemRWMtoLRSC; end diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 304733e8..09d76cb6 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -93,7 +93,6 @@ module lsu input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. ); - logic SquashSCM; logic DTLBPageFaultM; logic DTLBHitM; @@ -199,14 +198,14 @@ module lsu .TLBFlush(DTLBFlushM), .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), - .TLBHit(DTLBHitM), + //.TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), //.AtomicAccessM(AtomicMaskedM[1]), .AtomicAccessM(1'b0), .WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]), - .SquashBusAccess(), + //.SquashBusAccess(), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), .Cacheable(CacheableM), @@ -217,7 +216,7 @@ module lsu assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM, - .SquashSCM, .SquashSCW, .MemRWMtoDCache); + .SquashSCW, .MemRWMtoDCache); // *** BUG, this is most likely wrong assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM; diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 1995f09a..d8839817 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -67,7 +67,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries // Physical address outputs output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, - output logic TLBHit, output logic Cacheable, Idempotent, AtomicAllowed, // Faults @@ -77,11 +76,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries // PMA checker signals input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], - - output logic SquashBusAccess // *** send to privileged unit -// output logic [5:0] SelRegions - + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0] ); logic [`PA_BITS-1:0] TLBPAdr; @@ -92,6 +87,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries logic PMALoadAccessFaultM, PMPLoadAccessFaultM; logic PMAStoreAccessFaultM, PMPStoreAccessFaultM; logic Translate; + logic TLBHit; // only instantiate TLB if Virtual Memory is supported @@ -126,7 +122,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. - assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess; +// assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess; assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit); assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit); assign StoreAccessFaultM = (PMAStoreAccessFaultM | PMPStoreAccessFaultM) & ~(Translate & ~TLBHit); diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index 10572a0a..b253f6da 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -33,8 +33,8 @@ module csr #(parameter UIE_REGW = 12'b0 ) ( input logic clk, reset, - input logic FlushD, FlushE, FlushM, FlushW, - input logic StallD, StallE, StallM, StallW, + input logic FlushE, FlushM, FlushW, + input logic StallE, StallM, StallW, input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, From 2cfbd888fd94351c2882d39c15796b1355cd8c1b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 12:00:32 -0700 Subject: [PATCH 08/10] more lsu/ifu lint cleanup --- wally-pipelined/src/cache/dcache.sv | 10 ++-------- wally-pipelined/src/cache/icache.sv | 3 +-- wally-pipelined/src/ifu/ifu.sv | 19 +++++++------------ wally-pipelined/src/lsu/lsu.sv | 10 ++-------- .../src/wally/wallypipelinedhart.sv | 9 ++++----- wally-pipelined/testbench/testbench.sv | 2 +- 6 files changed, 17 insertions(+), 36 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 733f469f..a61a5acc 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -28,10 +28,7 @@ module dcache (input logic clk, input logic reset, - input logic StallM, input logic StallWtoDCache, - input logic FlushM, - input logic FlushW, // cpu side input logic [1:0] MemRWM, @@ -113,13 +110,12 @@ module dcache logic SRAMWordWriteEnableM; logic SRAMBlockWriteEnableM; logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; - logic SRAMWriteEnable; + //logic SRAMWriteEnable; logic [NUMWAYS-1:0] SRAMWayWriteEnable; logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; - logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic VictimDirty; logic SelUncached; logic [2**LOGWPL-1:0] MemPAdrDecodedW; @@ -144,9 +140,7 @@ module dcache logic SelFlush; logic VDWriteEnable; - logic AnyCPUReqM; logic FetchCountFlag; - logic PreCntEn; logic CntEn; logic CntReset; logic SelEvict; @@ -349,7 +343,7 @@ module dcache else assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b011 : Funct3M; endgenerate; - assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; + //assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; // controller diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 1e55e0da..0f684358 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -29,8 +29,7 @@ module icache ( // Basic pipeline stuff input logic clk, reset, - input logic StallF, StallD, - input logic FlushD, + input logic StallF, input logic [`PA_BITS-1:0] PCNextF, input logic [`PA_BITS-1:0] PCPF, // Data read in from the ebu unit diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 7a23800b..bdbf096d 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -37,8 +37,6 @@ module ifu ( output logic [`PA_BITS-1:0] InstrPAdrF, output logic InstrReadF, output logic ICacheStallF, - // Decode - output logic [`XLEN-1:0] PCD, // Execute output logic [`XLEN-1:0] PCLinkE, input logic PCSrcE, @@ -49,7 +47,7 @@ module ifu ( input logic RetM, TrapM, input logic [`XLEN-1:0] PrivilegedNextPCM, input logic InvalidateICacheM, - output logic [31:0] InstrD, InstrE, InstrM, InstrW, + output logic [31:0] InstrD, InstrM, output logic [`XLEN-1:0] PCM, output logic [4:0] InstrClassM, output logic BPPredDirWrongM, @@ -89,10 +87,13 @@ module ifu ( logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic PrivilegedChangePCM; logic IllegalCompInstrD; - logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCPF; + logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD; logic [`XLEN-3:0] PCPlusUpperF; logic CompressedF; logic [31:0] InstrRawD, FinalInstrRawF; + logic [31:0] InstrE; + logic [`XLEN-1:0] PCD; + localparam [31:0] nop = 32'h00000013; // instruction for NOP logic reset_q; // *** look at this later. @@ -100,14 +101,13 @@ module ifu ( logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. logic [`XLEN+1:0] PCFExt; - logic ITLBHitF; generate if (`XLEN==32) begin - assign PCPF = PCPFmmu[31:0]; + //assign PCPF = PCPFmmu[31:0]; assign PCNextFPhys = {{(`PA_BITS-`XLEN){1'b0}}, PCNextF}; end else begin - assign PCPF = {8'b0, PCPFmmu}; + //assign PCPF = {8'b0, PCPFmmu}; assign PCNextFPhys = PCNextF[`PA_BITS-1:0]; end endgenerate @@ -270,10 +270,8 @@ module ifu ( flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE); flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM); - // flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE); flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); - // flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later flopenrc #(5) InstrClassRegE(.clk(clk), .reset(reset), @@ -302,8 +300,5 @@ module ifu ( // *** redo this flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD); flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE); - // flopenr #(`XLEN) PCPMReg(clk, reset, ~StallM, PCLinkE, PCLinkM); - // /flopenr #(`XLEN) PCPWReg(clk, reset, ~StallW, PCLinkM, PCLinkW); - endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 09d76cb6..5c8f1261 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -94,7 +94,6 @@ module lsu ); logic DTLBPageFaultM; - logic DTLBHitM; logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache @@ -122,7 +121,7 @@ module lsu logic CommittedMfromDCache; logic PendingInterruptMtoDCache; - logic FlushWtoDCache; +// logic FlushWtoDCache; logic WalkerPageFaultM; logic AnyCPUReqM; @@ -198,20 +197,18 @@ module lsu .TLBFlush(DTLBFlushM), .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), - //.TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), //.AtomicAccessM(AtomicMaskedM[1]), .AtomicAccessM(1'b0), .WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]), - //.SquashBusAccess(), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(), - .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? + .*); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; @@ -241,10 +238,7 @@ module lsu dcache dcache(.clk(clk), .reset(reset), - .StallM(StallM), .StallWtoDCache(StallWtoDCache), - .FlushM(FlushM), - .FlushW(FlushWtoDCache), .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 1a4c826e..980166d9 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -63,15 +63,14 @@ module wallypipelinedhart ( logic [`XLEN-1:0] SrcAM; logic [2:0] Funct3E; // logic [31:0] InstrF; - logic [31:0] InstrD, InstrE, InstrM, InstrW; - logic [`XLEN-1:0] PCF, PCD, PCE, PCM, PCLinkE; + logic [31:0] InstrD, InstrM; + logic [`XLEN-1:0] PCF, PCE, PCM, PCLinkE; logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; logic [1:0] MemRWM; logic InstrValidM; logic InstrMisalignedFaultM; - logic DataMisalignedM; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM; logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM; @@ -86,7 +85,7 @@ module wallypipelinedhart ( logic SquashSCW; // floating point unit signals logic [2:0] FRM_REGW; - logic [4:0] RdE, RdM, RdW; + logic [4:0] RdM, RdW; logic FStallD; logic FWriteIntE, FWriteIntM, FWriteIntW; logic [`XLEN-1:0] FWriteDataE; @@ -178,7 +177,7 @@ module wallypipelinedhart ( .DCacheMiss, .DCacheAccess, .SquashSCW(SquashSCW), - .DataMisalignedM(DataMisalignedM), + //.DataMisalignedM(DataMisalignedM), .MemAdrE(MemAdrE), .MemAdrM(MemAdrM), .WriteDataM(WriteDataM), diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv index 5999f5d9..79945d2f 100644 --- a/wally-pipelined/testbench/testbench.sv +++ b/wally-pipelined/testbench/testbench.sv @@ -174,7 +174,7 @@ logic [3:0] dummy; instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.icache.FinalInstrRawF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests From c9e9cd4a6016e89d1a4b10773572ab654ddb5c9b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 12:10:13 -0700 Subject: [PATCH 09/10] more lsu/ifu lint cleanup --- wally-pipelined/src/cache/icache.sv | 5 +---- wally-pipelined/src/cache/icachefsm.sv | 2 +- wally-pipelined/src/ifu/ifu.sv | 2 +- wally-pipelined/src/lsu/lsu.sv | 2 +- wally-pipelined/src/mmu/mmu.sv | 1 - wally-pipelined/src/mmu/pmachecker.sv | 5 ----- wally-pipelined/src/mmu/pmpchecker.sv | 6 +----- 7 files changed, 5 insertions(+), 18 deletions(-) diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 0f684358..f1c0b29f 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -77,10 +77,9 @@ module icache logic FlushMem; logic ICacheMemWriteEnable; logic [BLOCKLEN-1:0] ICacheMemWriteData; - logic [`PA_BITS-1:0] PCTagF, PCNextIndexF; + logic [`PA_BITS-1:0] PCTagF; // Output signals from cache memory logic [31:0] ICacheMemReadData; - logic ICacheMemReadValid; logic ICacheReadEn; logic [BLOCKLEN-1:0] ReadLineF; @@ -101,7 +100,6 @@ module icache logic CntReset; logic [1:0] SelAdr; - logic SavePC; logic [INDEXLEN-1:0] RAdr; logic [NUMWAYS-1:0] VictimWay; logic LRUWriteEn; @@ -302,7 +300,6 @@ module icache .CntEn, .CntReset, .SelAdr, - .SavePC, .LRUWriteEn ); diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv index 49cbcb43..1d5ad0cd 100644 --- a/wally-pipelined/src/cache/icachefsm.sv +++ b/wally-pipelined/src/cache/icachefsm.sv @@ -61,7 +61,6 @@ module icachefsm #(parameter BLOCKLEN = 256) output logic CntEn, output logic CntReset, output logic [1:0] SelAdr, - output logic SavePC, output logic LRUWriteEn ); @@ -117,6 +116,7 @@ module icachefsm #(parameter BLOCKLEN = 256) statetype CurrState, NextState; logic PreCntEn; logic UnalignedSelect; + logic SavePC; // unused right now *** consider deleting // the FSM is always runing, do not stall. always_ff @(posedge clk, posedge reset) diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index bdbf096d..0582395b 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -87,7 +87,7 @@ module ifu ( logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic PrivilegedChangePCM; logic IllegalCompInstrD; - logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD; + logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; logic [`XLEN-3:0] PCPlusUpperF; logic CompressedF; logic [31:0] InstrRawD, FinalInstrRawF; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 5c8f1261..1b960488 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -45,7 +45,6 @@ module lsu input logic FlushDCacheM, output logic CommittedM, output logic SquashSCW, - output logic DataMisalignedM, output logic DCacheMiss, output logic DCacheAccess, @@ -94,6 +93,7 @@ module lsu ); logic DTLBPageFaultM; + logic DataMisalignedM; logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index d8839817..8c6614a1 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -80,7 +80,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries ); logic [`PA_BITS-1:0] TLBPAdr; - logic PMPSquashBusAccess, PMASquashBusAccess; // Translation lookaside buffer logic PMAInstrAccessFaultF, PMPInstrAccessFaultF; diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index a95252f3..904dd0ee 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -32,12 +32,8 @@ module pmachecker ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic [1:0] Size, - input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use. - output logic Cacheable, Idempotent, AtomicAllowed, - output logic PMASquashBusAccess, - output logic PMAInstrAccessFaultF, output logic PMALoadAccessFaultM, output logic PMAStoreAccessFaultM @@ -65,6 +61,5 @@ module pmachecker ( assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; - assign PMASquashBusAccess = PMAAccessFault; endmodule diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index 11cb7ccb..06cc9ea8 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -41,11 +41,7 @@ module pmpchecker ( // which we might not intend. input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], - input logic ExecuteAccessF, WriteAccessM, ReadAccessM, - - output logic PMPSquashBusAccess, - output logic PMPInstrAccessFaultF, output logic PMPLoadAccessFaultM, output logic PMPStoreAccessFaultM @@ -79,6 +75,6 @@ module pmpchecker ( assign PMPStoreAccessFaultM = EnforcePMP && WriteAccessM && ~|W; assign PMPLoadAccessFaultM = EnforcePMP && ReadAccessM && ~|R; - assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM; + //assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM; endmodule From 200eb453fb77dfb0f23376248d6f52e6346664fa Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 12:15:14 -0700 Subject: [PATCH 10/10] wrapping up lint cleanup; many unused signals removed --- wally-pipelined/regression/lint-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/lint-wally b/wally-pipelined/regression/lint-wally index 71edc0d5..67cc7a64 100755 --- a/wally-pipelined/regression/lint-wally +++ b/wally-pipelined/regression/lint-wally @@ -7,7 +7,7 @@ verilator=`which verilator` basepath=$(dirname $0)/.. for config in rv64g rv32g; do echo "$config linting..." - if !($verilator --lint-only --Wall "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then + if !($verilator --lint-only --Wall "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi