From de3f2547f4dd23935a118bdc89c86b209f6e9a1e Mon Sep 17 00:00:00 2001
From: Thomas Fleming <tfleming@hmc.edu>
Date: Thu, 4 Mar 2021 03:30:06 -0500
Subject: [PATCH] Install dtlb in dmem

---
 wally-pipelined/src/dmem/dmem.sv              | 19 +++++++++++++++++--
 wally-pipelined/src/ifu/ifu.sv                |  2 +-
 .../src/wally/wallypipelinedhart.sv           |  1 +
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv
index 58873932..aa4327c2 100644
--- a/wally-pipelined/src/dmem/dmem.sv
+++ b/wally-pipelined/src/dmem/dmem.sv
@@ -48,13 +48,28 @@ module dmem (
   // faults
   input  logic             DataAccessFaultM,
   output logic             LoadMisalignedFaultM, LoadAccessFaultM,
-  output logic             StoreMisalignedFaultM, StoreAccessFaultM
+  output logic             StoreMisalignedFaultM, StoreAccessFaultM,
+  // TLB management
+  //input logic  [`XLEN-1:0] PageTableEntryM,
+  //input logic              DTLBWriteM, DTLBFlushM,
+  // *** satp value will come from CSRs
+  // input logic [`XLEN-1:0] SATP,
+  output logic             DTLBMissM, DTLBHitM
 );
 
   logic             SquashSCM;
 
   // Initially no MMU
-  assign MemPAdrM = MemAdrM;
+  // *** temporary hack until we can figure out how to get actual satp value
+  // from priv unit -- Thomas F
+  logic [`XLEN-1:0] SATP = '0;
+  // *** temporary hack until walker is hooked up -- Thomas F
+  logic  [`XLEN-1:0] PageTableEntryM = '0;
+  logic DTLBFlushM = '0;
+  logic DTLBWriteM = '0;
+  tlb #(3) dtlb(clk, reset, SATP, MemAdrM, PageTableEntryM, DTLBWriteM,
+    DTLBFlushM, MemPAdrM, DTLBMissM, DTLBHitM);
+  //assign MemPAdrM = MemAdrM;
 
 	// Determine if an Unaligned access is taking place
 	always_comb
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index f5225d67..88e4f0be 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -52,7 +52,7 @@ module ifu (
   output logic             IllegalIEUInstrFaultD,
   output logic             InstrMisalignedFaultM,
   output logic [`XLEN-1:0] InstrMisalignedAdrM,
-  // TLB Management
+  // TLB management
   //input logic  [`XLEN-1:0] PageTableEntryF,
   //input logic              ITLBWriteF, ITLBFlushF,
   // *** satp value will come from CSRs
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 139a276e..ded4df3d 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -89,6 +89,7 @@ module wallypipelinedhart (
 
   // memory management unit signals
   logic             ITLBMissF, ITLBHitF;
+  logic             DTLBMissM, DTLBHitM;
 
   // bus interface to dmem
   logic             MemReadM, MemWriteM;