From dd004749568672d20ef5dcbdecb0cf34db353e84 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 28 Aug 2022 13:50:50 -0500 Subject: [PATCH] Created two new pma regions for dtim and irom. --- pipelined/src/ifu/ifu.sv | 5 +++-- pipelined/src/lsu/lsu.sv | 9 +++++---- pipelined/src/mmu/adrdecs.sv | 6 ++++-- pipelined/src/mmu/mmu.sv | 3 +-- pipelined/src/mmu/pmachecker.sv | 9 ++++----- pipelined/src/uncore/uncore.sv | 10 +++++----- 6 files changed, 22 insertions(+), 20 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 9dbe6ac9..2b9cfa44 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -156,7 +156,7 @@ module ifu ( mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1)) immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .PrivilegeModeW, .DisableTranslation(1'b0), .SelTIM(SelIROM), + .PrivilegeModeW, .DisableTranslation(1'b0), .VAdr(PCFExt), .Size(2'b10), .PTE(PTE), @@ -195,7 +195,8 @@ module ifu ( /* verilator lint_on WIDTH */ adrdec iromdec(PCFExt, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, 1'b1, 2'b10, 4'b1111, SelIROM); - assign NonIROMMemRWM = {~SelIROM, 1'b0}; + //assign NonIROMMemRWM = {~SelIROM, 1'b0}; + assign NonIROMMemRWM = 2'b10; irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF)); end else begin diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 3d2559ad..edc26f69 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -163,7 +163,7 @@ module lsu ( assign DisableTranslation = SelHPTW | FlushDCacheM; mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .PrivilegeModeW, .DisableTranslation, .SelTIM(SelDTIM), + .PrivilegeModeW, .DisableTranslation, .VAdr(PreLSUPAdrM), .Size(LSUFunct3M[1:0]), .PTE, @@ -212,8 +212,9 @@ module lsu ( assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS /* verilator lint_on WIDTH */ assign DTIMAccessRW = |MemRWM; - adrdec dtimdec(IEUAdrExtM, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, DTIMAccessRW, 2'b10, 4'b1111, SelDTIM); - assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected + adrdec dtimdec(IEUAdrExtM, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, DTIMAccessRW, 2'b10, 4'b1111, SelDTIM); // maybe we pull this out of the mmu? + //assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected + assign NonDTIMMemRWM = MemRWM; // *** fix dtim dtim(.clk, .reset, .MemRWM, .Adr(DTIMAdr), @@ -273,7 +274,7 @@ module lsu ( .BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), .HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM)); - assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping + assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping assign LSUHBURST = 3'b0; assign LSUTransComplete = LSUBusAck; assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index c6965bf3..163985e6 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -35,11 +35,13 @@ module adrdecs ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic AccessRW, AccessRX, AccessRWX, input logic [1:0] Size, - output logic [8:0] SelRegions + output logic [10:0] SelRegions ); localparam logic [3:0] SUPPORTED_SIZE = (`LLEN == 32 ? 4'b0111 : 4'b1111); // Determine which region of physical memory (if any) is being accessed + adrdec dtimdec(PhysicalAddress, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[10]); + adrdec iromdec(PhysicalAddress, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[9]); adrdec ddr4dec(PhysicalAddress, `EXT_MEM_BASE, `EXT_MEM_RANGE, `EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[8]); adrdec bootromdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[7]); adrdec uncoreramdec(PhysicalAddress, `UNCORE_RAM_BASE, `UNCORE_RAM_RANGE, `UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[6]); @@ -49,7 +51,7 @@ module adrdecs ( adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]); adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[1]); - assign SelRegions[0] = ~|(SelRegions[8:1]); // none of the regions are selected + assign SelRegions[0] = ~|(SelRegions[10:1]); // none of the regions are selected endmodule diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv index 389057df..dbf23e98 100644 --- a/pipelined/src/mmu/mmu.sv +++ b/pipelined/src/mmu/mmu.sv @@ -48,7 +48,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries // x1 - TLB is accessed for a write // 11 - TLB is accessed for both read and write input logic DisableTranslation, - input logic SelTIM, // access to DTIM or IROM; ignore other access checking // VAdr is the virtual/physical address from IEU or physical address from HPTW. // PhysicalAddress is selected to be PAdr when no translation or the translated VAdr (TLBPAdr) @@ -126,7 +125,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries /////////////////////////////////////////// pmachecker pmachecker(.PhysicalAddress, .Size, - .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .SelTIM, + .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .Cacheable, .Idempotent, .AtomicAllowed, .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM); diff --git a/pipelined/src/mmu/pmachecker.sv b/pipelined/src/mmu/pmachecker.sv index 078718d8..455f510d 100644 --- a/pipelined/src/mmu/pmachecker.sv +++ b/pipelined/src/mmu/pmachecker.sv @@ -38,7 +38,6 @@ module pmachecker ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic [1:0] Size, input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use. - input logic SelTIM, output logic Cacheable, Idempotent, AtomicAllowed, output logic PMAInstrAccessFaultF, output logic PMALoadAccessFaultM, @@ -47,7 +46,7 @@ module pmachecker ( logic PMAAccessFault; logic AccessRW, AccessRWX, AccessRX; - logic [8:0] SelRegions; + logic [10:0] SelRegions; // Determine what type of access is being made assign AccessRW = ReadAccessM | WriteAccessM; @@ -59,11 +58,11 @@ module pmachecker ( // Only non-core RAM/ROM memory regions are cacheable assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6]; - assign Idempotent = SelRegions[8] | SelRegions[6]; - assign AtomicAllowed = SelRegions[8] | SelRegions[6]; + assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6]; + assign AtomicAllowed = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6]; // Detect access faults - assign PMAAccessFault = (SelRegions[0] & ~SelTIM) & AccessRWX; + assign PMAAccessFault = (SelRegions[0]) & AccessRWX; assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault; assign PMAStoreAmoAccessFaultM = WriteAccessM & PMAAccessFault; diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 65fd8511..938ebf8c 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -67,9 +67,9 @@ module uncore ( logic [`XLEN-1:0] HREADRam, HREADSDC; - logic [8:0] HSELRegions; - logic HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC; - logic HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD; + logic [10:0] HSELRegions; + logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC; + logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD; logic HRESPRam, HRESPSDC; logic HREADYRam, HRESPSDCD; logic [`XLEN-1:0] HREADBootRom; @@ -93,7 +93,7 @@ module uncore ( adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions); // unswizzle HSEL signals - assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[8:1]; + assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[10:1]; // AHB -> APB bridge ahbapbbridge #(4) ahbapbbridge @@ -197,7 +197,7 @@ module uncore ( HSELNoneD; // don't lock up the bus if no region is being accessed // Address Decoder Delay (figure 4-2 in spec) - flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); + flopr #(11) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED); endmodule