From dc52f55aa6be83b8f351575debfbd5d796e26f4f Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 25 Aug 2022 18:34:39 -0700
Subject: [PATCH] Removed unused signals

---
 pipelined/src/lsu/busfsm.sv | 5 -----
 pipelined/src/lsu/lsu.sv    | 7 ++++---
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv
index 04fb6d9a..5c2b0c04 100644
--- a/pipelined/src/lsu/busfsm.sv
+++ b/pipelined/src/lsu/busfsm.sv
@@ -43,9 +43,7 @@ module busfsm #(parameter integer LOGWPL)
 
    output logic              BusStall,
    output logic              BusWrite,
-   output logic              SelBusWord,
    output logic              BusRead,
-   output logic              BusTransComplete,
    output logic [1:0]        HTRANS,
    output logic              BusCommitted
 );
@@ -85,7 +83,6 @@ module busfsm #(parameter integer LOGWPL)
 	endcase
   end
 
-  assign BusTransComplete = BusAck;
   assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & |RW) |
 					(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
 					(BusCurrState == STATE_BUS_UNCACHED_READ);
@@ -94,8 +91,6 @@ module busfsm #(parameter integer LOGWPL)
   assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) |
 							  (BusCurrState == STATE_BUS_UNCACHED_READ);
   assign BusCommitted = BusCurrState != STATE_BUS_READY;
-  assign SelBusWord = (BusCurrState == STATE_BUS_READY & RW[0]) |
-						   (BusCurrState == STATE_BUS_UNCACHED_WRITE);
 
   assign HTRANS = (BusRead | BusWrite) & (~BusAck) ? AHB_NONSEQ : AHB_IDLE; 
 endmodule
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 51a29cf3..bd9f8310 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -108,7 +108,6 @@ module lsu (
   logic                     InterlockStall;
   logic                     IgnoreRequestTLB;
   logic                     BusCommittedM, DCacheCommittedM;
-  logic                     SelBusWord;
   logic                     DataDAPageFaultM;
   logic [`XLEN-1:0]         IMWriteDataM, IMAWriteDataM;
   logic [`LLEN-1:0]         IMAFWriteDataM;
@@ -224,6 +223,7 @@ module lsu (
             
     if(`DCACHE) begin : dcache
       logic                SelUncachedAdr, DCacheBusAck;
+      logic                     SelBusWord;
 
       cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
@@ -257,12 +257,13 @@ module lsu (
       busfsm #(LOGBWPL) busfsm(
         .clk, .reset, .IgnoreRequest, .RW(LSURWM), 
         .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .BusStall, .BusWrite(LSUBusWrite), 
-        .SelBusWord, .BusRead(LSUBusRead), 
-        .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), 
+        .BusRead(LSUBusRead), 
+        .HTRANS(LSUHTRANS),  
         .BusCommitted(BusCommittedM));
     
       // *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
       assign LSUHBURST = 3'b0;
+      assign LSUTransComplete = BusAck;
       assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
       assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
     end