From db56a326c976f55264aec96b6e1362c113f180c0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Sep 2022 14:03:37 -0500 Subject: [PATCH] renamed multimanager to multicontroller. --- pipelined/regression/wave.do | 20 +++++++++---------- ...bmultimanager.sv => ahbmulticontroller.sv} | 20 +++++++++---------- ...rinputstage.sv => controllerinputstage.sv} | 10 +++++----- pipelined/src/wally/wallypipelinedcore.sv | 2 +- 4 files changed, 26 insertions(+), 26 deletions(-) rename pipelined/src/ebu/{ahbmultimanager.sv => ahbmulticontroller.sv} (94%) rename pipelined/src/ebu/{managerinputstage.sv => controllerinputstage.sv} (95%) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index ad5b5484..cd9cdef0 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -169,16 +169,16 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group AHB -expand -group multimanager -color Gold /testbench/dut/core/ebu/ebu/CurrState -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/dis -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/IFUActive -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/LSUActive -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/BeatCount -add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/BeatCountDelayed +add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/save +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/restore +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/dis +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/sel +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUActive +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUActive +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCountDelayed add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST diff --git a/pipelined/src/ebu/ahbmultimanager.sv b/pipelined/src/ebu/ahbmulticontroller.sv similarity index 94% rename from pipelined/src/ebu/ahbmultimanager.sv rename to pipelined/src/ebu/ahbmulticontroller.sv index dc9cbbdd..b6141737 100644 --- a/pipelined/src/ebu/ahbmultimanager.sv +++ b/pipelined/src/ebu/ahbmulticontroller.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// abhmultimanager +// abhmulticontroller // // Written: Ross Thompson August 29, 2022 // ross1728@gmail.com // Modified: // -// Purpose: AHB multi manager interface to merge LSU and IFU controls. +// Purpose: AHB multi controller interface to merge LSU and IFU controls. // See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0 // Arbitrates requests from instruction and data streams // Connects core to peripherals and I/O pins on SOC @@ -36,7 +36,7 @@ `include "wally-config.vh" -module ahbmultimanager +module ahbmulticontroller ( input logic clk, reset, // Signals from IFU @@ -110,20 +110,20 @@ module ahbmultimanager // inputs. Abritration scheme is LSU always goes first. // input stage IFU - managerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]), + controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]), .Request(IFUReq), .Active(IFUActive), .HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY)); // input stage LSU - managerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]), + controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]), .Request(LSUReq), .Active(LSUActive), .HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY)); - // output mux //*** rewrite for general number of managers. + // output mux //*** rewrite for general number of controllers. assign HADDR = sel[1] ? LSUHADDROut : sel[0] ? IFUHADDROut : '0; assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits assign HBURST = sel[1] ? LSUHBURSTOut : sel[0] ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. @@ -135,7 +135,7 @@ module ahbmultimanager // data phase muxing. This would be a mux if IFU wrote data. assign HWDATA = LSUHWDATA; assign HWSTRB = LSUHWSTRB; - // HRDATA is sent to all managers at the core level. + // HRDATA is sent to all controllers at the core level. // FSM decides if arbitration needed. Arbitration is held until the last beat of // a burst is completed. @@ -151,7 +151,7 @@ module ahbmultimanager endcase // This part is only used when burst mode is supported. - // Manager needs to count beats. + // Controller needs to count beats. flopenr #(4) BeatCountReg(.clk(HCLK), .reset(~HRESETn | CntReset | FinalBeat), @@ -190,12 +190,12 @@ module ahbmultimanager // basic arb always selects LSU when both // replace this block for more sophisticated arbitration as needed. - // Manager 0 (IFU) + // Controller 0 (IFU) assign save[0] = CurrState == IDLE & both; assign restore[0] = CurrState == ARBITRATE; assign dis[0] = CurrState == ARBITRATE; assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq; - // Manager 1 (LSU) + // Controller 1 (LSU) assign save[1] = 1'b0; assign restore[1] = 1'b0; assign dis[1] = 1'b0; diff --git a/pipelined/src/ebu/managerinputstage.sv b/pipelined/src/ebu/controllerinputstage.sv similarity index 95% rename from pipelined/src/ebu/managerinputstage.sv rename to pipelined/src/ebu/controllerinputstage.sv index ffacaff3..d302cc39 100644 --- a/pipelined/src/ebu/managerinputstage.sv +++ b/pipelined/src/ebu/controllerinputstage.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// manager input stage +// controller input stage // // Written: Ross Thompson August 31, 2022 // ross1728@gmail.com // Modified: // -// Purpose: AHB multi manager interface to merge LSU and IFU controls. +// Purpose: AHB multi controller interface to merge LSU and IFU controls. // See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0 // Arbitrates requests from instruction and data streams // Connects core to peripherals and I/O pins on SOC @@ -36,19 +36,19 @@ `include "wally-config.vh" -module managerinputstage +module controllerinputstage (input logic HCLK, input logic HRESETn, input logic Save, Restore, Disable, output logic Request, Active, - // manager input + // controller input input logic HWRITEin, input logic [2:0] HSIZEin, input logic [2:0] HBURSTin, input logic [1:0] HTRANSin, input logic [`PA_BITS-1:0] HADDRin, output logic HREADYOut, - // manager output + // controller output output logic HWRITEOut, output logic [2:0] HSIZEOut, output logic [2:0] HBURSTOut, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 95ff25ec..dd7567a7 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -288,7 +288,7 @@ module wallypipelinedcore ( // *** Ross: please make EBU conditional when only supporting internal memories if(`BUS) begin : ebu - ahbmultimanager ebu(// IFU connections + ahbmulticontroller ebu(// IFU connections .clk, .reset, // IFU interface .IFUHADDR,