From dac011c1d2fd5eb635dafa8235e250a96d3a6030 Mon Sep 17 00:00:00 2001
From: Alec Vercruysse <vercruysse.alec@gmail.com>
Date: Wed, 29 Mar 2023 13:04:00 -0700
Subject: [PATCH] icache coverage improvements by simplifying logic

---
 src/cache/cache.sv    | 19 +++++++++++++------
 src/cache/cacheLRU.sv |  8 +++++---
 2 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index da7f8327..3dac0c56 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -168,14 +168,21 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
     assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
   end
   assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
-  assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
 
-  // Merge write data into fetched cache line for store miss
-  for(index = 0; index < LINELEN/8; index++) begin
-    mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
-      .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
+  if(!READ_ONLY_CACHE) begin:WriteSelLogic
+    // Merge write data into fetched cache line for store miss
+    for(index = 0; index < LINELEN/8; index++) begin
+       mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
+         .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
+    end
+    assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
   end
-   
+  else
+    begin:WriteSelLogic
+       // No need for this mux if the cache does not handle writes.
+       assign LineWriteData = FetchBuffer;
+       assign LineByteMask = '1;
+    end
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Flush logic
   /////////////////////////////////////////////////////////////////////////////////////////////
diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 05e26f4b..78080794 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -98,7 +98,9 @@ module cacheLRU
     assign LRUUpdate[t1] = LRUUpdate[s] & WayEncoded[r];
   end
 
-  mux2 #(1) LRUMuxes[NUMWAYS-2:0](CurrLRU, ~WayExpanded, LRUUpdate, NextLRU);
+  // The root node of the LRU tree will always be selected in LRUUpdate. No mux needed.
+  assign NextLRU[NUMWAYS-2] = ~WayExpanded[NUMWAYS-2];
+  mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]);
 
   // Compute next victim way.
   for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin
@@ -128,8 +130,8 @@ module cacheLRU
   always_ff @(posedge clk) begin
     if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
     if(CacheEn) begin
-      if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
-      else if (LRUWriteEn & ~FlushStage) begin 
+      // if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
+      if (LRUWriteEn & ~FlushStage) begin 
         LRUMemory[PAdr] <= NextLRU;
       end
       if(LRUWriteEn & ~FlushStage & (PAdr == CacheSet))