From 6031269de88c21f271f997d7a72e0a6b856c3733 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 3 Mar 2021 18:17:53 -0600 Subject: [PATCH 1/7] Implemented fix disucssed with Elizabeth --- wally-pipelined/regression/wally-coremark.do | 20 +++++++++---------- .../testbench/testbench-coremark.sv | 3 +++ 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index 056b34cb..f3205ae5 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -52,23 +52,23 @@ add wave -divider #add wave /testbench/dut/hart/FlushM #add wave /testbench/dut/hart/FlushW -add wave -divider +add wave -divider Fetch add wave -hex /testbench/dut/hart/ifu/PCF add wave -hex /testbench/dut/hart/ifu/InstrF add wave /testbench/InstrFName -add wave -divider +add wave -divider Decode add wave -hex /testbench/dut/hart/ifu/PCD add wave -hex /testbench/dut/hart/ifu/InstrD add wave /testbench/InstrDName -add wave -divider +add wave -divider Execute add wave -hex /testbench/dut/hart/ifu/PCE add wave -hex /testbench/dut/hart/ifu/InstrE add wave /testbench/InstrEName -add wave -divider +add wave -divider Memory add wave -hex /testbench/dut/hart/ifu/PCM add wave -hex /testbench/dut/hart/ifu/InstrM add wave /testbench/InstrMName -add wave -divider +add wave -divider Write add wave -hex /testbench/dut/hart/ifu/PCW add wave -hex /testbench/dut/hart/ifu/InstrW add wave /testbench/InstrWName @@ -76,7 +76,7 @@ add wave /testbench/InstrWName #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE #add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE #add wave /testbench/dut/hart/ieu/dp/PCSrcE -add wave -divider +add wave -divider Regfile #add wave /testbench/dut/uncore/dtim/memwrite #add wave -hex /testbench/dut/uncore/HADDR #add wave -hex /testbench/dut/uncore/HWDATA @@ -88,9 +88,9 @@ add wave -divider #add wave -hex /testbench/dut/hart/ieu/dp/RdW #add wave -hex -r /testbench/* add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* +add wave -divider Misc add wave -divider -add wave -divider -add wave -hex -r /testbench/dut/hart/ebu/ReadDataW +#add wave -hex -r /testbench/dut/uncore/dtim/RAM -- Set Wave Output Items TreeUpdate [SetDefaultTree] @@ -106,6 +106,6 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -run 3000 -#run -all +#run 3000 +run -all #quit diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index 9f458567..a8d53715 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -66,6 +66,7 @@ module testbench(); dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests + integer j; initial begin totalerrors = 0; @@ -73,6 +74,8 @@ module testbench(); memfilename = tests[0]; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); + for(j=1911; j < 65535; j = j+1) + dut.uncore.dtim.RAM[j] = 64'b0; reset = 1; # 22; reset = 0; end // generate clock to sequence tests From 08a7f6ec254f0bc3e1d67eee2164b11fbf112969 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 01:27:05 -0600 Subject: [PATCH 2/7] In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches --- wally-pipelined/config/coremark/wally-config.vh | 7 +++---- wally-pipelined/regression/wally-coremark.do | 14 +++++++++----- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index 906373f9..de4d0366 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -56,8 +56,7 @@ `define MEM_VIRTMEM 0 // Address space -//`define RESET_VECTOR 64'h0000000080000000 -`define RESET_VECTOR 64'h0000000000000000 +`define RESET_VECTOR 64'h0000000080000000 // Bus Interface width `define AHBW 64 @@ -66,8 +65,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define TIMBASE 32'h00000000 -`define TIMRANGE 32'h0007FFFF +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h00007FFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index f3205ae5..2627a596 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -76,7 +76,7 @@ add wave /testbench/InstrWName #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE #add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE #add wave /testbench/dut/hart/ieu/dp/PCSrcE -add wave -divider Regfile +add wave -divider Regfile_signals #add wave /testbench/dut/uncore/dtim/memwrite #add wave -hex /testbench/dut/uncore/HADDR #add wave -hex /testbench/dut/uncore/HWDATA @@ -86,11 +86,14 @@ add wave -divider Regfile #add wave /testbench/dut/hart/ieu/dp/RegWriteW #add wave -hex /testbench/dut/hart/ieu/dp/ResultW #add wave -hex /testbench/dut/hart/ieu/dp/RdW -#add wave -hex -r /testbench/* add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* +add wave -divider Regfile_itself +add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf +add wave -divider RAM +add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -#add wave -hex -r /testbench/dut/uncore/dtim/RAM +add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] @@ -106,6 +109,7 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -#run 3000 -run -all +#run 7402000 +run 2780 +#run -all #quit From 6ebb79abe07d3622f895a32148ad13813a642981 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 05:58:18 -0600 Subject: [PATCH 3/7] Linux CoreMark is operational --- wally-pipelined/config/coremark/wally-config.vh | 6 +++--- wally-pipelined/regression/wally-coremark.do | 6 +++--- wally-pipelined/testbench/testbench-coremark.sv | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index de4d0366..4ee5448a 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -56,7 +56,7 @@ `define MEM_VIRTMEM 0 // Address space -`define RESET_VECTOR 64'h0000000080000000 +`define RESET_VECTOR 64'h00000000000100b0 // Bus Interface width `define AHBW 64 @@ -65,8 +65,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h00007FFF +`define TIMBASE 32'h00000000 +`define TIMRANGE 32'hFFFFFFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index 2627a596..ea63e2ae 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -93,7 +93,7 @@ add wave -divider RAM add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -add wave -hex -r /testbench/* +#add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] @@ -110,6 +110,6 @@ set DefaultRadix hexadecimal -- Run the Simulation #run 7402000 -run 2780 -#run -all +#run 10500 +run -all #quit diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index a8d53715..fbec9f46 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -48,7 +48,7 @@ module testbench(); // pick tests based on modes supported initial - tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"}; + tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.elf.memfile", "1000"}; string signame, memfilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -74,7 +74,7 @@ module testbench(); memfilename = tests[0]; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); - for(j=1911; j < 65535; j = j+1) + for(j=18710; j < 65535; j = j+1) dut.uncore.dtim.RAM[j] = 64'b0; reset = 1; # 22; reset = 0; end From 396dc61564852886b9f2b54a25b89e350a2d91cf Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 07:44:33 -0600 Subject: [PATCH 4/7] Linux CoreMark and baremetal CoreMark split into two separate tests/configs --- .../config/coremark_bare/wally-config.vh | 89 ++++++++ .../regression/wally-coremark_bare.do | 115 ++++++++++ .../testbench/testbench-coremark_bare.sv | 215 ++++++++++++++++++ 3 files changed, 419 insertions(+) create mode 100644 wally-pipelined/config/coremark_bare/wally-config.vh create mode 100644 wally-pipelined/regression/wally-coremark_bare.do create mode 100644 wally-pipelined/testbench/testbench-coremark_bare.sv diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh new file mode 100644 index 00000000..53f3a5f5 --- /dev/null +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -0,0 +1,89 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 64 + +//`define MISA (32'h00000104) +`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12) +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +`define ZCSR_SUPPORTED 1 +`define ZCOUNTERS_SUPPORTED 1 +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define MEM_DCACHE 0 +`define MEM_DTIM 1 +`define MEM_ICACHE 0 +`define MEM_VIRTMEM 0 + +// Address space +`define RESET_VECTOR 64'h0000000080000000 + +// Bus Interface width +`define AHBW 64 + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h000FFFFF +`define CLINTBASE 32'h02000000 +`define CLINTRANGE 32'h0000FFFF +`define GPIOBASE 32'h10012000 +`define GPIORANGE 32'h000000FF +`define UARTBASE 32'h10000000 +`define UARTRANGE 32'h00000007 + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 0 + + +// Hardware configuration +`define UART_PRESCALE 1 + +/* verilator lint_off STMTDLY */ +/* verilator lint_off WIDTH */ +/* verilator lint_off ASSIGNDLY */ +/* verilator lint_off PINCONNECTEMPTY */ diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do new file mode 100644 index 00000000..4bbf4e66 --- /dev/null +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -0,0 +1,115 @@ +# wally-coremark.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# Use this wally-coremark.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-coremark.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-coremark.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# default to config/coremark, but allow this to be overridden at the command line. For example: +vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../src/*/*.sv -suppress 2583 + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt +acc work.testbench -o workopt +vsim workopt + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave /testbench/clk +add wave /testbench/reset +add wave -divider +#add wave /testbench/dut/hart/ebu/IReadF +#add wave /testbench/dut/hart/DataStall +#add wave /testbench/dut/hart/InstrStall +#add wave /testbench/dut/hart/StallF +#add wave /testbench/dut/hart/StallD +#add wave /testbench/dut/hart/FlushD +#add wave /testbench/dut/hart/FlushE +#add wave /testbench/dut/hart/FlushM +#add wave /testbench/dut/hart/FlushW + +add wave -divider Fetch +add wave -hex /testbench/dut/hart/ifu/PCF +add wave -hex /testbench/dut/hart/ifu/InstrF +add wave /testbench/InstrFName +add wave -divider Decode +add wave -hex /testbench/dut/hart/ifu/PCD +add wave -hex /testbench/dut/hart/ifu/InstrD +add wave /testbench/InstrDName +add wave -divider Execute +add wave -hex /testbench/dut/hart/ifu/PCE +add wave -hex /testbench/dut/hart/ifu/InstrE +add wave /testbench/InstrEName +add wave -divider Memory +add wave -hex /testbench/dut/hart/ifu/PCM +add wave -hex /testbench/dut/hart/ifu/InstrM +add wave /testbench/InstrMName +add wave -divider Write +add wave -hex /testbench/dut/hart/ifu/PCW +add wave -hex /testbench/dut/hart/ifu/InstrW +add wave /testbench/InstrWName +#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE +#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE +#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE +#add wave /testbench/dut/hart/ieu/dp/PCSrcE +add wave -divider Regfile_signals +#add wave /testbench/dut/uncore/dtim/memwrite +#add wave -hex /testbench/dut/uncore/HADDR +#add wave -hex /testbench/dut/uncore/HWDATA +#add wave -divider +#add wave -hex /testbench/dut/hart/ifu/PCW +#add wave /testbench/InstrWName +#add wave /testbench/dut/hart/ieu/dp/RegWriteW +#add wave -hex /testbench/dut/hart/ieu/dp/ResultW +#add wave -hex /testbench/dut/hart/ieu/dp/RdW +add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* +add wave -divider Regfile_itself +add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf +add wave -divider RAM +add wave -hex -r /testbench/dut/uncore/dtim/RAM +add wave -divider Misc +add wave -divider +#add wave -hex -r /testbench/* + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {100 ps} +configure wave -namecolwidth 250 +configure wave -valuecolwidth 120 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +set DefaultRadix hexadecimal + +-- Run the Simulation +#run 7402000 +#run 10500 +run -all +#quit diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv new file mode 100644 index 00000000..04332fbb --- /dev/null +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -0,0 +1,215 @@ +/////////////////////////////////////////// +// testbench-imperas.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: Wally Testbench and helper modules +// Applies test programs from the Imperas suite +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// +`include "wally-config.vh" +module testbench(); + logic clk; + logic reset; + int test, i, errors, totalerrors; + logic [31:0] sig32[0:10000]; + logic [`XLEN-1:0] signature[0:10000]; + logic [`XLEN-1:0] testadr; + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [`XLEN-1:0] meminit; + string tests[]; + logic [`AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; + logic [31:0] HADDR; + logic [`AHBW-1:0] HWDATA; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic HCLK, HRESETn; + + // pick tests based on modes supported + initial + tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"}; + string signame, memfilename; + logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic UARTSin, UARTSout; + // instantiate device to be tested + assign GPIOPinsIn = 0; + assign UARTSin = 1; + assign HREADYEXT = 1; + assign HRESPEXT = 0; + assign HRDATAEXT = 0; + wallypipelinedsoc dut(.*); + // Track names of instructions + instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, + dut.hart.ifu.InstrF, + dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, + dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + // initialize tests + integer j; + initial + begin + totalerrors = 0; + // read test vectors into memory + memfilename = tests[0]; + $readmemh(memfilename, dut.imem.RAM); + $readmemh(memfilename, dut.uncore.dtim.RAM); + for(j=2371; j < 65535; j = j+1) + dut.uncore.dtim.RAM[j] = 64'b0; + reset = 1; # 22; reset = 0; + end + // generate clock to sequence tests + always + begin + clk = 1; # 5; clk = 0; # 5; + end + +endmodule +/* verilator lint_on STMTDLY */ +/* verilator lint_on WIDTH */ +module instrTrackerTB( + input logic clk, reset, FlushE, + input logic [31:0] InstrF, InstrD, + input logic [31:0] InstrE, InstrM, + input logic [31:0] InstrW, + output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + + // stage Instr to Writeback for visualization + instrNameDecTB fdec(InstrF, InstrFName); + instrNameDecTB ddec(InstrD, InstrDName); + instrNameDecTB edec(InstrE, InstrEName); + instrNameDecTB mdec(InstrM, InstrMName); + instrNameDecTB wdec(InstrW, InstrWName); +endmodule +// decode the instruction name, to help the test bench +module instrNameDecTB( + input logic [31:0] instr, + output string name); + logic [6:0] op; + logic [2:0] funct3; + logic [6:0] funct7; + logic [11:0] imm; + assign op = instr[6:0]; + assign funct3 = instr[14:12]; + assign funct7 = instr[31:25]; + assign imm = instr[31:20]; + // it would be nice to add the operands to the name + // create another variable called decoded + always_comb + casez({op, funct3}) + 10'b0000000_000: name = "BAD"; + 10'b0000011_000: name = "LB"; + 10'b0000011_001: name = "LH"; + 10'b0000011_010: name = "LW"; + 10'b0000011_011: name = "LD"; + 10'b0000011_100: name = "LBU"; + 10'b0000011_101: name = "LHU"; + 10'b0000011_110: name = "LWU"; + 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH"; + else name = "ADDI"; + 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI"; + else name = "ILLEGAL"; + 10'b0010011_010: name = "SLTI"; + 10'b0010011_011: name = "SLTIU"; + 10'b0010011_100: name = "XORI"; + 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI"; + else if (funct7[6:1] == 6'b010000) name = "SRAI"; + else name = "ILLEGAL"; + 10'b0010011_110: name = "ORI"; + 10'b0010011_111: name = "ANDI"; + 10'b0010111_???: name = "AUIPC"; + 10'b0100011_000: name = "SB"; + 10'b0100011_001: name = "SH"; + 10'b0100011_010: name = "SW"; + 10'b0100011_011: name = "SD"; + 10'b0011011_000: name = "ADDIW"; + 10'b0011011_001: name = "SLLIW"; + 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW"; + else if (funct7 == 7'b0100000) name = "SRAIW"; + else name = "ILLEGAL"; + 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW"; + else if (funct7 == 7'b0100000) name = "SUBW"; + else if (funct7 == 7'b0000001) name = "MULW"; + else name = "ILLEGAL"; + 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW"; + else if (funct7 == 7'b0000001) name = "DIVW"; + else name = "ILLEGAL"; + 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW"; + else if (funct7 == 7'b0100000) name = "SRAW"; + else if (funct7 == 7'b0000001) name = "DIVUW"; + else name = "ILLEGAL"; + 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW"; + else name = "ILLEGAL"; + 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW"; + else name = "ILLEGAL"; + 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; + else if (funct7 == 7'b0000001) name = "MUL"; + else if (funct7 == 7'b0100000) name = "SUB"; + else name = "ILLEGAL"; + 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL"; + else if (funct7 == 7'b0000001) name = "MULH"; + else name = "ILLEGAL"; + 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT"; + else if (funct7 == 7'b0000001) name = "MULHSU"; + else name = "ILLEGAL"; + 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU"; + else if (funct7 == 7'b0000001) name = "MULHU"; + else name = "ILLEGAL"; + 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR"; + else if (funct7 == 7'b0000001) name = "DIV"; + else name = "ILLEGAL"; + 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; + else if (funct7 == 7'b0000001) name = "DIVU"; + else if (funct7 == 7'b0100000) name = "SRA"; + else name = "ILLEGAL"; + 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR"; + else if (funct7 == 7'b0000001) name = "REM"; + else name = "ILLEGAL"; + 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND"; + else if (funct7 == 7'b0000001) name = "REMU"; + else name = "ILLEGAL"; + 10'b0110111_???: name = "LUI"; + 10'b1100011_000: name = "BEQ"; + 10'b1100011_001: name = "BNE"; + 10'b1100011_100: name = "BLT"; + 10'b1100011_101: name = "BGE"; + 10'b1100011_110: name = "BLTU"; + 10'b1100011_111: name = "BGEU"; + 10'b1100111_000: name = "JALR"; + 10'b1101111_???: name = "JAL"; + 10'b1110011_000: if (imm == 0) name = "ECALL"; + else if (imm == 1) name = "EBREAK"; + else if (imm == 2) name = "URET"; + else if (imm == 258) name = "SRET"; + else if (imm == 770) name = "MRET"; + else name = "ILLEGAL"; + 10'b1110011_001: name = "CSRRW"; + 10'b1110011_010: name = "CSRRS"; + 10'b1110011_011: name = "CSRRC"; + 10'b1110011_101: name = "CSRRWI"; + 10'b1110011_110: name = "CSRRSI"; + 10'b1110011_111: name = "CSRRCI"; + 10'b0001111_???: name = "FENCE"; + default: name = "ILLEGAL"; + endcase +endmodule From 8f1584ca04c0a760adbaec6858005cbaaefe56b4 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 07:45:40 -0600 Subject: [PATCH 5/7] Edited assemby of bare-metal coremark to make it run --- wally-pipelined/regression/wally-coremark_bare.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 4bbf4e66..fdb40a05 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -110,6 +110,6 @@ set DefaultRadix hexadecimal -- Run the Simulation #run 7402000 -#run 10500 +#run 12750 run -all #quit From 06be82fc679128caf31b676d17e89de0575dbec8 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 07:47:07 -0600 Subject: [PATCH 6/7] Added stop to coremark_bare testbench --- wally-pipelined/testbench/testbench-coremark_bare.sv | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 04332fbb..529a6b98 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -83,6 +83,14 @@ module testbench(); begin clk = 1; # 5; clk = 0; # 5; end + always @(negedge clk) + begin + if (dut.hart.priv.ebreakM) begin + #20; + $display("Code ended with ebreakM"); + $stop; + end + end endmodule /* verilator lint_on STMTDLY */