From da2dca981687bfdee623266174de972683458c08 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 7 Feb 2022 21:59:18 -0600
Subject: [PATCH] Removed VDWriteEnable.

---
 pipelined/src/cache/cache.sv    |  6 +-----
 pipelined/src/cache/cachefsm.sv |  6 +-----
 pipelined/src/cache/cacheway.sv | 11 +++++------
 3 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index cd2a2dfb..474a9156 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -99,10 +99,8 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
   logic [NUMWAYS-1:0] 						NextFlushWay;
   logic 									FlushWayCntEn;
   logic 									FlushWayCntRst;  
-  logic 									VDWriteEnable;
   logic 									SelEvict;
   logic 									LRUWriteEn;
-  logic [NUMWAYS-1:0] 						VDWriteEnableWay;
   logic 									SelFlush;
   logic                                     ResetOrFlushAdr, ResetOrFlushWay;
   logic [NUMWAYS-1:0]                       WayHitSaved, WayHitRaw;
@@ -124,7 +122,6 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
   cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](
     .clk, .reset, .RAdr, .PAdr,
 		.WriteEnable(SRAMWayWriteEnable),
-		.VDWriteEnable(VDWriteEnableWay),
 		.WriteWordEnable(SRAMWordEnable),
 		.TagWriteEnable(SRAMLineWayWriteEnable), 
 		.WriteData(SRAMWriteData),
@@ -191,7 +188,6 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
 			  .en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}),
 			  .d(NextFlushWay), .q(FlushWay));
   assign FlushWayFlag = FlushWay[NUMWAYS-1];
-  assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};
   assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
 
   assign SelectedWay = SelFlush ? FlushWay : (SRAMLineWriteEnable ? VictimWay : WayHit);
@@ -215,5 +211,5 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
 		.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
 		.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
         .save, .restore,
-		.VDWriteEnable, .LRUWriteEn);
+        .LRUWriteEn);
 endmodule 
diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index cbde7e01..63c45286 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -75,10 +75,7 @@ module cachefsm
    output logic       FlushAdrCntRst,
    output logic       FlushWayCntRst,
    output logic       save,
-   output logic       restore,
-   output logic       VDWriteEnable
-
-   );
+   output logic       restore);
   
   logic [1:0]         PreSelAdr;
   logic               resetDelay;
@@ -201,7 +198,6 @@ module cachefsm
                                (CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) |
                                (CurrState == STATE_MISS_WRITE_WORD);
   assign SRAMLineWriteEnable = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
-  assign VDWriteEnable = (CurrState == STATE_FLUSH_CLEAR_DIRTY);
   assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
   assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) |
                       (CurrState == STATE_MISS_READ_WORD_DELAY) |
diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
index 3d61e09d..7cb2084a 100644
--- a/pipelined/src/cache/cacheway.sv
+++ b/pipelined/src/cache/cacheway.sv
@@ -38,7 +38,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   input logic [$clog2(NUMLINES)-1:0] RAdr,
   input logic [`PA_BITS-1:0]         PAdr,
   input logic                        WriteEnable,
-  input logic                        VDWriteEnable, 
   input logic [LINELEN/`XLEN-1:0]    WriteWordEnable,
   input logic                        TagWriteEnable,
   input logic [LINELEN-1:0]          WriteData,
@@ -69,7 +68,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   logic [$clog2(NUMLINES)-1:0] 		  RAdrD;
   logic 							  SetValidD, ClearValidD;
   logic 							  SetDirtyD, ClearDirtyD;
-  logic 							  WriteEnableD, VDWriteEnableD;
+  logic 							  WriteEnableD;
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Tag Array
@@ -113,8 +112,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
 	end
   // *** consider revisiting whether these delays are the best option? 
   flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
-  flop #(4) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable, VDWriteEnable},
-    {SetValidD, ClearValidD, WriteEnableD, VDWriteEnableD});
+  flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable},
+    {SetValidD, ClearValidD, WriteEnableD});
   assign Valid = ValidBits[RAdrD];
 
   /////////////////////////////////////////////////////////////////////////////////////////////
@@ -125,8 +124,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   if (DIRTY_BITS) begin:dirty
     always_ff @(posedge clk) begin
       if (reset)                                              DirtyBits        <= #1 {NUMLINES{1'b0}};
-      else if (SetDirtyD   & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b1;
-      else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b0;
+      else if (SetDirtyD) DirtyBits[RAdrD] <= #1 1'b1;
+      else if (ClearDirtyD) DirtyBits[RAdrD] <= #1 1'b0;
     end
     flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
     assign Dirty = DirtyBits[RAdrD];