diff --git a/config/rv32e/rv32e-config.vh b/config/rv32e/rv32e-config.vh index 24011b15..4701b69f 100644 --- a/config/rv32e/rv32e-config.vh +++ b/config/rv32e/rv32e-config.vh @@ -26,18 +26,19 @@ //////////////////////////////////////////////////////////////////////////////////////////////// localparam PA_BITS = 34; -localparam AHBW = 32; -localparam XLEN = 32; -localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ); -localparam BUS_SUPPORTED = 1'b1; -localparam ZICSR_SUPPORTED = 1'b0; +//localparam AHBW = 32; +//localparam XLEN = 32; +//localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ); +////localparam BUS_SUPPORTED = 1'b1; +//localparam ZICSR_SUPPORTED = 1'b0; localparam M_SUPPORTED = 1'b0; -localparam ZMMUL_SUPPORTED = 1'b0; localparam F_SUPPORTED = 1'b0; -localparam PMP_ENTRIES = 0; +//localparam ZMMUL_SUPPORTED = 1'b0; +//localparam F_SUPPORTED = 1'b0; +//localparam PMP_ENTRIES = 0; localparam LLEN = 32; -localparam FPGA = 1'b0; -localparam QEMU = 1'b0; +//localparam FPGA = 1'b0; +//localparam QEMU = 1'b0; // //VPN_SEGMENT_BITS: (LLEN == 32 ? 10 : 9), // `include "test-shared.vh" localparam FLEN = 32; @@ -106,35 +107,35 @@ localparam WFI_TIMEOUT_BIT = 16; // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits localparam DTIM_SUPPORTED = 1'b0; -localparam DTIM_BASE = ; 34'h80000000 -localparam DTIM_RANGE = ; 34'h007FFFFF +localparam DTIM_BASE = 34'h80000000; +localparam DTIM_RANGE = 34'h007FFFFF; localparam IROM_SUPPORTED = 1'b0; -localparam IROM_BASE = ; 34'h80000000 -localparam IROM_RANGE = ; 34'h007FFFFF +localparam IROM_BASE = 34'h80000000; +localparam IROM_RANGE = 34'h007FFFFF; localparam BOOTROM_SUPPORTED = 1'b1; -localparam BOOTROM_BASE = ; 34'h00001000 -localparam BOOTROM_RANGE = ; 34'h00000FFF +localparam BOOTROM_BASE = 34'h00001000; +localparam BOOTROM_RANGE = 34'h00000FFF; localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam UNCORE_RAM_BASE = ; 34'h80000000 -localparam UNCORE_RAM_RANGE = ; 34'h07FFFFFF +localparam UNCORE_RAM_BASE = 34'h80000000; +localparam UNCORE_RAM_RANGE = 34'h07FFFFFF; localparam EXT_MEM_SUPPORTED = 1'b0; -localparam EXT_MEM_BASE = ; 34'h80000000 -localparam EXT_MEM_RANGE = ; 34'h07FFFFFF +localparam EXT_MEM_BASE = 34'h80000000; +localparam EXT_MEM_RANGE = 34'h07FFFFFF; localparam CLINT_SUPPORTED = 1'b0; -localparam CLINT_BASE = ; 34'h02000000 +localparam CLINT_BASE = 34'h02000000; localparam CLINT_RANGE = 34'h0000FFFF; localparam GPIO_SUPPORTED = 1'b0; -localparam GPIO_BASE = ; 34'h10060000 -localparam GPIO_RANGE = ; 34'h000000FF +localparam GPIO_BASE = 34'h10060000; +localparam GPIO_RANGE = 34'h000000FF; localparam UART_SUPPORTED = 1'b0; -localparam UART_BASE = ; 34'h10000000 -localparam UART_RANGE = ; 34'h00000007 +localparam UART_BASE = 34'h10000000; +localparam UART_RANGE = 34'h00000007; localparam PLIC_SUPPORTED = 1'b0; -localparam PLIC_BASE = ; 34'h0C000000 -localparam PLIC_RANGE = ; 34'h03FFFFFF +localparam PLIC_BASE = 34'h0C000000; +localparam PLIC_RANGE = 34'h03FFFFFF; localparam SDC_SUPPORTED = 1'b0; -localparam SDC_BASE = ; 34'h00012100 -localparam SDC_RANGE = ; 34'h0000001F +localparam SDC_BASE = 34'h00012100; +localparam SDC_RANGE = 34'h0000001F; // Bus Interface width localparam AHBW = 32; @@ -150,7 +151,7 @@ localparam UART_PRESCALE = 1; // Interrupt configuration localparam PLIC_NUM_SRC = 10; // comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); localparam PLIC_GPIO_ID = 3; localparam PLIC_UART_ID = 10; @@ -163,8 +164,8 @@ localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; // FPU division architecture -localparam RADIX = 32'h4; -localparam DIVCOPIES = 32'h4; +localparam RADIX = 4; +localparam DIVCOPIES = 4; // bit manipulation localparam ZBA_SUPPORTED = 0; @@ -174,4 +175,4 @@ localparam ZBS_SUPPORTED = 0; // Memory synthesis configuration localparam USE_SRAM = 0; - */ \ No newline at end of file + \ No newline at end of file diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index b95ef0a0..84deb79e 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -1,20 +1,3 @@ -/* parameter cvw_t P = '{ - PA_BITS : PA_BITS, - XLEN: XLEN, - AHBW: AHBW, - MISA: MISA, - BUS_SUPPORTED: BUS_SUPPORTED, - ZICSR_SUPPORTED: ZICSR_SUPPORTED, - M_SUPPORTED: M_SUPPORTED, - ZMMUL_SUPPORTED: ZMMUL_SUPPORTED, - F_SUPPORTED: F_SUPPORTED, - PMP_ENTRIES: PMP_ENTRIES, - LLEN: LLEN, - FPGA: FPGA, - QEMU: QEMU, - VPN_SEGMENT_BITS: VPN_SEGMENT_BITS, - FLEN: FLEN -}, */ // Populate parameter structure with values specific to the current configuration @@ -82,7 +65,6 @@ parameter cvw_t P = '{ SDC_SUPPORTED : SDC_SUPPORTED, SDC_BASE : SDC_BASE, SDC_RANGE : SDC_RANGE, - AHBW : AHBW, GPIO_LOOPBACK_TEST : GPIO_LOOPBACK_TEST, UART_PRESCALE : UART_PRESCALE , PLIC_NUM_SRC : PLIC_NUM_SRC, diff --git a/src/wally/cvw.sv b/src/wally/cvw.sv index 40926ca3..2b47d360 100644 --- a/src/wally/cvw.sv +++ b/src/wally/cvw.sv @@ -78,7 +78,7 @@ typedef struct packed { byte PMP_ENTRIES; // Address space - logic [63:0] RESET_VECTOR; + logic [31:0] RESET_VECTOR; // WFI Timeout Wait byte WFI_TIMEOUT_BIT; @@ -87,38 +87,35 @@ typedef struct packed { // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits logic DTIM_SUPPORTED; - logic [55:0] DTIM_BASE; - logic [55:0] DTIM_RANGE; + logic [33:0] DTIM_BASE; + logic [33:0] DTIM_RANGE; logic IROM_SUPPORTED; - logic [55:0] IROM_BASE; - logic [55:0] IROM_RANGE; + logic [33:0] IROM_BASE; + logic [33:0] IROM_RANGE; logic BOOTROM_SUPPORTED; - logic [55:0] BOOTROM_BASE; - logic [55:0] BOOTROM_RANGE; + logic [33:0] BOOTROM_BASE; + logic [33:0] BOOTROM_RANGE; logic UNCORE_RAM_SUPPORTED; - logic [55:0] UNCORE_RAM_BASE; - logic [55:0] UNCORE_RAM_RANGE; + logic [33:0] UNCORE_RAM_BASE; + logic [33:0] UNCORE_RAM_RANGE; logic EXT_MEM_SUPPORTED; - logic [55:0] EXT_MEM_BASE; - logic [55:0] EXT_MEM_RANGE; + logic [33:0] EXT_MEM_BASE; + logic [33:0] EXT_MEM_RANGE; logic CLINT_SUPPORTED; - logic [55:0] CLINT_BASE; - logic [55:0] CLINT_RANGE; + logic [33:0] CLINT_BASE; + logic [33:0] CLINT_RANGE; logic GPIO_SUPPORTED; - logic [55:0] GPIO_BASE; - logic [55:0] GPIO_RANGE; + logic [33:0] GPIO_BASE; + logic [33:0] GPIO_RANGE; logic UART_SUPPORTED; - logic [55:0] UART_BASE; - logic [55:0] UART_RANGE; + logic [33:0] UART_BASE; + logic [33:0] UART_RANGE; logic PLIC_SUPPORTED; - logic [55:0] PLIC_BASE; - logic [55:0] PLIC_RANGE; + logic [33:0] PLIC_BASE; + logic [33:0] PLIC_RANGE; logic SDC_SUPPORTED; - logic [55:0] SDC_BASE; - logic [55:0] SDC_RANGE; - -// Bus Interface width - byte AHBW; + logic [33:0] SDC_BASE; + logic [33:0] SDC_RANGE; // Test modes @@ -130,8 +127,7 @@ typedef struct packed { // Interrupt configuration byte PLIC_NUM_SRC; -// comment out the following if >=32 sources - byte PLIC_NUM_SRC_LT_32; // *** make automatic + logic PLIC_NUM_SRC_LT_32; byte PLIC_GPIO_ID; byte PLIC_UART_ID; diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 1503b676..53ba3a68 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -34,21 +34,12 @@ module wallypipelinedcore #(parameter cvw_t P) ( input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, // Bus Interface -<<<<<<< HEAD input logic [P.AHBW-1:0] HRDATA, input logic HREADY, HRESP, output logic HCLK, HRESETn, output logic [P.PA_BITS-1:0] HADDR, output logic [P.AHBW-1:0] HWDATA, output logic [P.XLEN/8-1:0] HWSTRB, -======= - input logic [`AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [`PA_BITS-1:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -66,7 +57,6 @@ module wallypipelinedcore #(parameter cvw_t P) ( logic IntDivE, W64E; logic CSRReadM, CSRWriteM, PrivilegedM; logic [1:0] AtomicM; -<<<<<<< HEAD logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; logic [P.XLEN-1:0] SrcAM; logic [2:0] Funct3E; @@ -78,19 +68,6 @@ module wallypipelinedcore #(parameter cvw_t P) ( logic [P.XLEN-1:0] UnalignedPCNextF, PC2NextF; logic [1:0] MemRWM; logic InstrValidD, InstrValidE, InstrValidM; -======= - logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; - logic [`XLEN-1:0] SrcAM; - logic [2:0] Funct3E; - logic [31:0] InstrD; - logic [31:0] InstrM, InstrOrigM; - logic [`XLEN-1:0] PCSpillF, PCE, PCLinkE; - logic [`XLEN-1:0] PCM; - logic [`XLEN-1:0] CSRReadValW, MDUResultW; - logic [`XLEN-1:0] UnalignedPCNextF, PC2NextF; - logic [1:0] MemRWM; - logic InstrValidD, InstrValidE, InstrValidM; ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a logic InstrMisalignedFaultM; logic IllegalBaseInstrD, IllegalFPUInstrD, IllegalIEUFPUInstrD; logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; @@ -108,55 +85,32 @@ module wallypipelinedcore #(parameter cvw_t P) ( logic [4:0] RdE, RdM, RdW; logic FPUStallD; logic FWriteIntE; -<<<<<<< HEAD logic [P.FLEN-1:0] FWriteDataM; logic [P.XLEN-1:0] FIntResM; logic [P.XLEN-1:0] FCvtIntResW; -======= - logic [`FLEN-1:0] FWriteDataM; - logic [`XLEN-1:0] FIntResM; - logic [`XLEN-1:0] FCvtIntResW; ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a logic FCvtIntW; logic FDivBusyE; logic FRegWriteM; logic FCvtIntStallD; logic FpLoadStoreM; logic [4:0] SetFflagsM; -<<<<<<< HEAD logic [P.XLEN-1:0] FIntDivResultW; -======= - logic [`XLEN-1:0] FIntDivResultW; ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a // memory management unit signals logic ITLBWriteF; logic ITLBMissF; -<<<<<<< HEAD logic [P.XLEN-1:0] SATP_REGW; -======= - logic [`XLEN-1:0] SATP_REGW; ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; logic [1:0] STATUS_MPP, STATUS_FS; logic [1:0] PrivilegeModeW; -<<<<<<< HEAD logic [P.XLEN-1:0] PTE; -======= - logic [`XLEN-1:0] PTE; ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a logic [1:0] PageType; logic sfencevmaM, WFIStallM; logic SelHPTW; // PMA checker signals -<<<<<<< HEAD var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0]; -======= - var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]; - var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a // IMem stalls logic IFUStallF; @@ -164,7 +118,6 @@ module wallypipelinedcore #(parameter cvw_t P) ( // cpu lsu interface logic [2:0] Funct3M; -<<<<<<< HEAD logic [P.XLEN-1:0] IEUAdrE; logic [P.XLEN-1:0] WriteDataM; logic [P.XLEN-1:0] IEUAdrM; @@ -173,16 +126,6 @@ module wallypipelinedcore #(parameter cvw_t P) ( // AHB ifu interface logic [P.PA_BITS-1:0] IFUHADDR; -======= - logic [`XLEN-1:0] IEUAdrE; - logic [`XLEN-1:0] WriteDataM; - logic [`XLEN-1:0] IEUAdrM; - logic [`LLEN-1:0] ReadDataW; - logic CommittedM; - - // AHB ifu interface - logic [`PA_BITS-1:0] IFUHADDR; ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a logic [2:0] IFUHBURST; logic [1:0] IFUHTRANS; logic [2:0] IFUHSIZE; @@ -190,15 +133,9 @@ module wallypipelinedcore #(parameter cvw_t P) ( logic IFUHREADY; // AHB LSU interface -<<<<<<< HEAD logic [P.PA_BITS-1:0] LSUHADDR; logic [P.XLEN-1:0] LSUHWDATA; logic [P.XLEN/8-1:0] LSUHWSTRB; -======= - logic [`PA_BITS-1:0] LSUHADDR; - logic [`XLEN-1:0] LSUHWDATA; - logic [`XLEN/8-1:0] LSUHWSTRB; ->>>>>>> 46e08410112c38dc213a034105f96f6979e1680a logic LSUHWRITE; logic LSUHREADY; diff --git a/src/wally/wallypipelinedsoc_32e.sv b/src/wally/wallypipelinedsoc_32e.sv index eccb5490..c5056283 100644 --- a/src/wally/wallypipelinedsoc_32e.sv +++ b/src/wally/wallypipelinedsoc_32e.sv @@ -51,9 +51,9 @@ module wallypipelinedsoc_32e ( output logic HREADY, // I/O Interface input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOPinsIn, // inputs from GPIO - output logic [31:0] GPIOPinsOut, // output values for GPIO - output logic [31:0] GPIOPinsEn, // output enables for GPIO + input logic [31:0] GPIOIN, // inputs from GPIO + output logic [31:0] GPIOOUT, // output values for GPIO + output logic [31:0] GPIOEN, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output input logic SDCCmdIn, // SDC Command input