From d8ddda760b21f6e4b50e3d153bc40c1d13b9779b Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 00:37:46 +0000 Subject: [PATCH] deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test --- pipelined/regression/regression-wally | 2 +- pipelined/testbench/testbench.sv | 3 - pipelined/testbench/tests.vh | 37 +- .../rv64i_m/privilege/Makefrag | 26 +- .../WALLY-CSR-PERMISSIONS-M.reference_output | 1008 ++++ .../WALLY-CSR-PERMISSIONS-S.reference_output | 336 ++ .../references/WALLY-MARCHID.reference_output | 392 ++ .../references/WALLY-MCAUSE.reference_output | 208 + .../references/WALLY-MEDELEG.reference_output | 120 + .../references/WALLY-MHARTID.reference_output | 392 ++ .../references/WALLY-MIMPID.reference_output | 392 ++ .../references/WALLY-MSTATUS.reference_output | 16 + .../references/WALLY-MTVEC.reference_output | 96 + .../WALLY-MVENDORID.reference_output | 392 ++ .../references/WALLY-SCAUSE.reference_output | 128 + .../references/WALLY-STVEC.reference_output | 64 + .../references/WALLY-UCAUSE.reference_output | 80 + .../privilege/src/WALLY-CSR-PERMISSIONS-M.S | 5265 +++++++++++++++++ .../privilege/src/WALLY-CSR-PERMISSIONS-S.S | 2627 ++++++++ .../rv64i_m/privilege/src/WALLY-MARCHID.S | 3778 ++++++++++++ .../rv64i_m/privilege/src/WALLY-MCAUSE.S | 2324 ++++++++ .../rv64i_m/privilege/src/WALLY-MEDELEG.S | 3675 ++++++++++++ .../rv64i_m/privilege/src/WALLY-MHARTID.S | 3778 ++++++++++++ .../rv64i_m/privilege/src/WALLY-MIMPID.S | 3778 ++++++++++++ .../rv64i_m/privilege/src/WALLY-MSTATUS.S | 433 ++ .../rv64i_m/privilege/src/WALLY-MTVEC.S | 1455 +++++ .../rv64i_m/privilege/src/WALLY-MVENDORID.S | 3778 ++++++++++++ .../rv64i_m/privilege/src/WALLY-SCAUSE.S | 1396 +++++ .../rv64i_m/privilege/src/WALLY-STVEC.S | 1022 ++++ .../rv64i_m/privilege/src/WALLY-UCAUSE.S | 459 ++ 30 files changed, 37431 insertions(+), 29 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-S.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MARCHID.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MCAUSE.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MEDELEG.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MHARTID.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIMPID.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MSTATUS.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MTVEC.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MVENDORID.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-SCAUSE.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-STVEC.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-UCAUSE.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-M.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIMPID.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index a35684b3..17782b9d 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -62,7 +62,7 @@ tc = TestCase( grepstr="400100000 instructions") configs.append(tc) -tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"] +tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"] for test in tests64gc: tc = TestCase( name=test, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 226b2f28..7c582280 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -33,8 +33,6 @@ `include "tests.vh" module testbench; - parameter TESTSPERIPH = 0; // set to 0 for regression - parameter TESTSPRIV = 0; // set to 0 for regression parameter DEBUG=0; parameter TEST="none"; @@ -89,7 +87,6 @@ logic [3:0] dummy; "arch64m": if (`M_SUPPORTED) tests = arch64m; "arch64d": if (`D_SUPPORTED) tests = arch64d; "imperas64i": tests = imperas64i; - "imperas64p": tests = imperas64p; // "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64d": if (`D_SUPPORTED) tests = imperas64d; diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index c90484f3..e8f8fd12 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -846,28 +846,6 @@ string imperas32f[] = '{ "rv64BP/dhrystone", "1000000" }; - string imperas64p[] = '{ - `MYIMPERASTEST, - "rv64p/WALLY-MSTATUS", "2000", - "rv64p/WALLY-MCAUSE", "3000", - "rv64p/WALLY-SCAUSE", "2000", - "rv64p/WALLY-MEPC", "5000", - "rv64p/WALLY-SEPC", "4000", - "rv64p/WALLY-MTVAL", "6000", - "rv64p/WALLY-STVAL", "4000", - "rv64p/WALLY-MTVEC", "2000", - "rv64p/WALLY-STVEC", "2000", - "rv64p/WALLY-MARCHID", "4000", - "rv64p/WALLY-MIMPID", "4000", - "rv64p/WALLY-MHARTID", "4000", - "rv64p/WALLY-MVENDORID", "4000", - "rv64p/WALLY-MIE", "3000", - "rv64p/WALLY-MEDELEG", "4000", - "rv64p/WALLY-IP", "2000", - "rv64p/WALLY-CSR-PERMISSIONS-M", "5000", - "rv64p/WALLY-CSR-PERMISSIONS-S", "3000" - }; - string imperas32p[] = '{ `MYIMPERASTEST, "rv32p/WALLY-MSTATUS", "2000", @@ -1481,7 +1459,20 @@ string imperas32f[] = '{ "rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0", "rv64i_m/privilege/WALLY-misa-01", "40A0", "rv64i_m/privilege/WALLY-scratch-01", "40A0", - "rv64i_m/privilege/WALLY-sscratch-s-01", "40A0" + "rv64i_m/privilege/WALLY-sscratch-s-01", "40A0", + "rv64i_m/privilege/WALLY-MSTATUS", "2090", + "rv64i_m/privilege/WALLY-MCAUSE", "3090", + "rv64i_m/privilege/WALLY-SCAUSE", "2090", + "rv64i_m/privilege/WALLY-UCAUSE", "2090", + "rv64i_m/privilege/WALLY-MTVEC", "2090", + "rv64i_m/privilege/WALLY-STVEC", "2090", + "rv64i_m/privilege/WALLY-MEDELEG", "4090", + "rv64i_m/privilege/WALLY-MARCHID", "4090", + "rv64i_m/privilege/WALLY-MHARTID", "4090", + "rv64i_m/privilege/WALLY-MIMPID", "4090", + "rv64i_m/privilege/WALLY-MVENDORID", "4090", + "rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "5090", + "rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "3090" }; string wally64periph[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 395374e8..bdfaaa65 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -36,11 +36,33 @@ rv64i_sc_tests = \ WALLY-CSR-permission-u-01 \ WALLY-misa-01 \ WALLY-scratch-01 \ - WALLY-sscratch-s-01 + WALLY-sscratch-s-01 \ +# Don't simulate these because they rely on SoC features that Wally does not offer. target_tests_nosim = \ WALLY-PMA \ - WALLY-PERIPH + WALLY-PERIPH \ + WALLY-MSTATUS \ + WALLY-MCAUSE \ + WALLY-SCAUSE \ + WALLY-UCAUSE \ + WALLY-MTVEC \ + WALLY-STVEC \ + WALLY-MEDELEG \ + WALLY-MARCHID \ + WALLY-MHARTID \ + WALLY-MIMPID \ + WALLY-MVENDORID \ + WALLY-CSR-PERMISSIONS-M \ + WALLY-CSR-PERMISSIONS-S + # Have all 0's in references! + #WALLY-MEPC \ + #WALLY-SEPC \ + #WALLY-MTVAL \ + #WALLY-STVAL \ + # Otherwise Broken for Unknown Reasons + #WALLY-MIE \ + #WALLY-IP \ rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output new file mode 100644 index 00000000..ce736a35 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output @@ 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a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MARCHID.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MARCHID.reference_output new file mode 100644 index 00000000..15b0e063 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MARCHID.reference_output @@ -0,0 +1,392 @@ +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 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../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-CSR-PERMISSIONS-M.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:21.723799// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mstatus_0 + csrw mtvec, x1 + + csrr x23, mstatus + + j _j_test_s_mstatus_0 + + _m_trap_from_s_mstatus_0: + bnez x30, _j_end_s_mstatus_0 + + csrr x25, mcause + csrr x24, mstatus + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mstatus_0: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo0: + li x25, 0xDEADBEA7 + + csrrw x1, mstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo1: + li x25, 0xDEADBEA7 + + csrrw x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo2: + li x25, 0xDEADBEA7 + + csrrwi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo3: + li x25, 0xDEADBEA7 + + csrrs x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo4: + li x25, 0xDEADBEA7 + + csrrc x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo5: + li x25, 0xDEADBEA7 + + csrrsi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo6: + li x25, 0xDEADBEA7 + + csrrci x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mstatus_0: + + li x30, 0 + la x1, _m_trap_from_u_mstatus_7 + csrw mtvec, x1 + + csrr x23, mstatus + + j _j_test_u_mstatus_7 + + _m_trap_from_u_mstatus_7: + bnez x30, _j_end_u_mstatus_7 + + csrr x25, mcause + csrr x24, mstatus + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mstatus_7: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo7: + li x25, 0xDEADBEA7 + + csrrw x1, mstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo8: + li x25, 0xDEADBEA7 + + csrrw x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo9: + li x25, 0xDEADBEA7 + + csrrwi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo10: + li x25, 0xDEADBEA7 + + csrrs x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo11: + li x25, 0xDEADBEA7 + + csrrc x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo12: + li x25, 0xDEADBEA7 + + csrrsi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo13: + li x25, 0xDEADBEA7 + + csrrci x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mstatus_7: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mstatus_14 + csrw mtvec, x1 + + csrr x23, mstatus + + j _j_test_s_mstatus_14 + + _m_trap_from_s_mstatus_14: + bnez x30, _j_end_s_mstatus_14 + + csrr x25, mcause + csrr x24, mstatus + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mstatus_14: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo14: + li x25, 0xDEADBEA7 + + csrrw x1, mstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo15: + li x25, 0xDEADBEA7 + + csrrw x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo16: + li x25, 0xDEADBEA7 + + csrrwi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo17: + li x25, 0xDEADBEA7 + + csrrs x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo18: + li x25, 0xDEADBEA7 + + csrrc x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo19: + li x25, 0xDEADBEA7 + + csrrsi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo20: + li x25, 0xDEADBEA7 + + csrrci x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mstatus_14: + + li x30, 0 + la x1, _m_trap_from_u_mstatus_21 + csrw mtvec, x1 + + csrr x23, mstatus + + j _j_test_u_mstatus_21 + + _m_trap_from_u_mstatus_21: + bnez x30, _j_end_u_mstatus_21 + + csrr x25, mcause + csrr x24, mstatus + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mstatus_21: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo21: + li x25, 0xDEADBEA7 + + csrrw x1, mstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo22: + li x25, 0xDEADBEA7 + + csrrw x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo23: + li x25, 0xDEADBEA7 + + csrrwi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo24: + li x25, 0xDEADBEA7 + + csrrs x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo25: + li x25, 0xDEADBEA7 + + csrrc x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo26: + li x25, 0xDEADBEA7 + + csrrsi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo27: + li x25, 0xDEADBEA7 + + csrrci x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mstatus_21: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_medeleg_28 + csrw mtvec, x1 + + csrr x23, medeleg + + j _j_test_s_medeleg_28 + + _m_trap_from_s_medeleg_28: + bnez x30, _j_end_s_medeleg_28 + + csrr x25, mcause + csrr x24, medeleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_medeleg_28: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo28: + li x25, 0xDEADBEA7 + + csrrw x1, medeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo30: + li x25, 0xDEADBEA7 + + csrrw x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo32: + li x25, 0xDEADBEA7 + + csrrwi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo34: + li x25, 0xDEADBEA7 + + csrrs x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo36: + li x25, 0xDEADBEA7 + + csrrc x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo38: + li x25, 0xDEADBEA7 + + csrrsi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo40: + li x25, 0xDEADBEA7 + + csrrci x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_medeleg_28: + + li x30, 0 + la x1, _m_trap_from_u_medeleg_42 + csrw mtvec, x1 + + csrr x23, medeleg + + j _j_test_u_medeleg_42 + + _m_trap_from_u_medeleg_42: + bnez x30, _j_end_u_medeleg_42 + + csrr x25, mcause + csrr x24, medeleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_medeleg_42: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo42: + li x25, 0xDEADBEA7 + + csrrw x1, medeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo44: + li x25, 0xDEADBEA7 + + csrrw x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo46: + li x25, 0xDEADBEA7 + + csrrwi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo48: + li x25, 0xDEADBEA7 + + csrrs x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo50: + li x25, 0xDEADBEA7 + + csrrc x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo52: + li x25, 0xDEADBEA7 + + csrrsi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo54: + li x25, 0xDEADBEA7 + + csrrci x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_medeleg_42: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_medeleg_56 + csrw mtvec, x1 + + csrr x23, medeleg + + j _j_test_s_medeleg_56 + + _m_trap_from_s_medeleg_56: + bnez x30, _j_end_s_medeleg_56 + + csrr x25, mcause + csrr x24, medeleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_medeleg_56: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo56: + li x25, 0xDEADBEA7 + + csrrw x1, medeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo58: + li x25, 0xDEADBEA7 + + csrrw x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo60: + li x25, 0xDEADBEA7 + + csrrwi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo62: + li x25, 0xDEADBEA7 + + csrrs x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo64: + li x25, 0xDEADBEA7 + + csrrc x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo66: + li x25, 0xDEADBEA7 + + csrrsi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo68: + li x25, 0xDEADBEA7 + + csrrci x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_medeleg_56: + + li x30, 0 + la x1, _m_trap_from_u_medeleg_70 + csrw mtvec, x1 + + csrr x23, medeleg + + j _j_test_u_medeleg_70 + + _m_trap_from_u_medeleg_70: + bnez x30, _j_end_u_medeleg_70 + + csrr x25, mcause + csrr x24, medeleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_medeleg_70: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo70: + li x25, 0xDEADBEA7 + + csrrw x1, medeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo72: + li x25, 0xDEADBEA7 + + csrrw x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo74: + li x25, 0xDEADBEA7 + + csrrwi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo76: + li x25, 0xDEADBEA7 + + csrrs x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo78: + li x25, 0xDEADBEA7 + + csrrc x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo80: + li x25, 0xDEADBEA7 + + csrrsi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo82: + li x25, 0xDEADBEA7 + + csrrci x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_medeleg_70: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mideleg_84 + csrw mtvec, x1 + + csrr x23, mideleg + + j _j_test_s_mideleg_84 + + _m_trap_from_s_mideleg_84: + bnez x30, _j_end_s_mideleg_84 + + csrr x25, mcause + csrr x24, mideleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mideleg_84: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo84: + li x25, 0xDEADBEA7 + + csrrw x1, mideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo86: + li x25, 0xDEADBEA7 + + csrrw x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo88: + li x25, 0xDEADBEA7 + + csrrwi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo90: + li x25, 0xDEADBEA7 + + csrrs x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo92: + li x25, 0xDEADBEA7 + + csrrc x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo94: + li x25, 0xDEADBEA7 + + csrrsi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo96: + li x25, 0xDEADBEA7 + + csrrci x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mideleg_84: + + li x30, 0 + la x1, _m_trap_from_u_mideleg_98 + csrw mtvec, x1 + + csrr x23, mideleg + + j _j_test_u_mideleg_98 + + _m_trap_from_u_mideleg_98: + bnez x30, _j_end_u_mideleg_98 + + csrr x25, mcause + csrr x24, mideleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mideleg_98: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo98: + li x25, 0xDEADBEA7 + + csrrw x1, mideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo100: + li x25, 0xDEADBEA7 + + csrrw x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo102: + li x25, 0xDEADBEA7 + + csrrwi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo104: + li x25, 0xDEADBEA7 + + csrrs x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo106: + li x25, 0xDEADBEA7 + + csrrc x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo108: + li x25, 0xDEADBEA7 + + csrrsi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo110: + li x25, 0xDEADBEA7 + + csrrci x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mideleg_98: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mideleg_112 + csrw mtvec, x1 + + csrr x23, mideleg + + j _j_test_s_mideleg_112 + + _m_trap_from_s_mideleg_112: + bnez x30, _j_end_s_mideleg_112 + + csrr x25, mcause + csrr x24, mideleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mideleg_112: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo112: + li x25, 0xDEADBEA7 + + csrrw x1, mideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo114: + li x25, 0xDEADBEA7 + + csrrw x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo116: + li x25, 0xDEADBEA7 + + csrrwi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo118: + li x25, 0xDEADBEA7 + + csrrs x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo120: + li x25, 0xDEADBEA7 + + csrrc x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo122: + li x25, 0xDEADBEA7 + + csrrsi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo124: + li x25, 0xDEADBEA7 + + csrrci x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mideleg_112: + + li x30, 0 + la x1, _m_trap_from_u_mideleg_126 + csrw mtvec, x1 + + csrr x23, mideleg + + j _j_test_u_mideleg_126 + + _m_trap_from_u_mideleg_126: + bnez x30, _j_end_u_mideleg_126 + + csrr x25, mcause + csrr x24, mideleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mideleg_126: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo126: + li x25, 0xDEADBEA7 + + csrrw x1, mideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo128: + li x25, 0xDEADBEA7 + + csrrw x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo130: + li x25, 0xDEADBEA7 + + csrrwi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo132: + li x25, 0xDEADBEA7 + + csrrs x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo134: + li x25, 0xDEADBEA7 + + csrrc x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo136: + li x25, 0xDEADBEA7 + + csrrsi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo138: + li x25, 0xDEADBEA7 + + csrrci x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mideleg_126: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mie_140 + csrw mtvec, x1 + + csrr x23, mie + + j _j_test_s_mie_140 + + _m_trap_from_s_mie_140: + bnez x30, _j_end_s_mie_140 + + csrr x25, mcause + csrr x24, mie + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mie_140: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo140: + li x25, 0xDEADBEA7 + + csrrw x1, mie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo142: + li x25, 0xDEADBEA7 + + csrrw x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo144: + li x25, 0xDEADBEA7 + + csrrwi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo146: + li x25, 0xDEADBEA7 + + csrrs x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo148: + li x25, 0xDEADBEA7 + + csrrc x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo150: + li x25, 0xDEADBEA7 + + csrrsi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo152: + li x25, 0xDEADBEA7 + + csrrci x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mie_140: + + li x30, 0 + la x1, _m_trap_from_u_mie_154 + csrw mtvec, x1 + + csrr x23, mie + + j _j_test_u_mie_154 + + _m_trap_from_u_mie_154: + bnez x30, _j_end_u_mie_154 + + csrr x25, mcause + csrr x24, mie + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mie_154: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo154: + li x25, 0xDEADBEA7 + + csrrw x1, mie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo156: + li x25, 0xDEADBEA7 + + csrrw x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo158: + li x25, 0xDEADBEA7 + + csrrwi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo160: + li x25, 0xDEADBEA7 + + csrrs x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo162: + li x25, 0xDEADBEA7 + + csrrc x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo164: + li x25, 0xDEADBEA7 + + csrrsi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo166: + li x25, 0xDEADBEA7 + + csrrci x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mie_154: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mie_168 + csrw mtvec, x1 + + csrr x23, mie + + j _j_test_s_mie_168 + + _m_trap_from_s_mie_168: + bnez x30, _j_end_s_mie_168 + + csrr x25, mcause + csrr x24, mie + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mie_168: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo168: + li x25, 0xDEADBEA7 + + csrrw x1, mie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo170: + li x25, 0xDEADBEA7 + + csrrw x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo172: + li x25, 0xDEADBEA7 + + csrrwi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo174: + li x25, 0xDEADBEA7 + + csrrs x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo176: + li x25, 0xDEADBEA7 + + csrrc x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo178: + li x25, 0xDEADBEA7 + + csrrsi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo180: + li x25, 0xDEADBEA7 + + csrrci x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mie_168: + + li x30, 0 + la x1, _m_trap_from_u_mie_182 + csrw mtvec, x1 + + csrr x23, mie + + j _j_test_u_mie_182 + + _m_trap_from_u_mie_182: + bnez x30, _j_end_u_mie_182 + + csrr x25, mcause + csrr x24, mie + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mie_182: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo182: + li x25, 0xDEADBEA7 + + csrrw x1, mie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo184: + li x25, 0xDEADBEA7 + + csrrw x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo186: + li x25, 0xDEADBEA7 + + csrrwi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo188: + li x25, 0xDEADBEA7 + + csrrs x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo190: + li x25, 0xDEADBEA7 + + csrrc x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo192: + li x25, 0xDEADBEA7 + + csrrsi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo194: + li x25, 0xDEADBEA7 + + csrrci x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mie_182: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mtvec_196 + csrw mtvec, x1 + + csrr x23, mtvec + + j _j_test_s_mtvec_196 + + _m_trap_from_s_mtvec_196: + bnez x30, _j_end_s_mtvec_196 + + csrr x25, mcause + csrr x24, mtvec + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mtvec_196: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo196: + li x25, 0xDEADBEA7 + + csrrw x1, mtvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo198: + li x25, 0xDEADBEA7 + + csrrw x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo200: + li x25, 0xDEADBEA7 + + csrrwi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo202: + li x25, 0xDEADBEA7 + + csrrs x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo204: + li x25, 0xDEADBEA7 + + csrrc x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo206: + li x25, 0xDEADBEA7 + + csrrsi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo208: + li x25, 0xDEADBEA7 + + csrrci x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mtvec_196: + + li x30, 0 + la x1, _m_trap_from_u_mtvec_210 + csrw mtvec, x1 + + csrr x23, mtvec + + j _j_test_u_mtvec_210 + + _m_trap_from_u_mtvec_210: + bnez x30, _j_end_u_mtvec_210 + + csrr x25, mcause + csrr x24, mtvec + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mtvec_210: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo210: + li x25, 0xDEADBEA7 + + csrrw x1, mtvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo212: + li x25, 0xDEADBEA7 + + csrrw x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo214: + li x25, 0xDEADBEA7 + + csrrwi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo216: + li x25, 0xDEADBEA7 + + csrrs x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo218: + li x25, 0xDEADBEA7 + + csrrc x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo220: + li x25, 0xDEADBEA7 + + csrrsi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo222: + li x25, 0xDEADBEA7 + + csrrci x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mtvec_210: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mtvec_224 + csrw mtvec, x1 + + csrr x23, mtvec + + j _j_test_s_mtvec_224 + + _m_trap_from_s_mtvec_224: + bnez x30, _j_end_s_mtvec_224 + + csrr x25, mcause + csrr x24, mtvec + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mtvec_224: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo224: + li x25, 0xDEADBEA7 + + csrrw x1, mtvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo226: + li x25, 0xDEADBEA7 + + csrrw x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo228: + li x25, 0xDEADBEA7 + + csrrwi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo230: + li x25, 0xDEADBEA7 + + csrrs x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo232: + li x25, 0xDEADBEA7 + + csrrc x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo234: + li x25, 0xDEADBEA7 + + csrrsi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo236: + li x25, 0xDEADBEA7 + + csrrci x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mtvec_224: + + li x30, 0 + la x1, _m_trap_from_u_mtvec_238 + csrw mtvec, x1 + + csrr x23, mtvec + + j _j_test_u_mtvec_238 + + _m_trap_from_u_mtvec_238: + bnez x30, _j_end_u_mtvec_238 + + csrr x25, mcause + csrr x24, mtvec + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mtvec_238: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo238: + li x25, 0xDEADBEA7 + + csrrw x1, mtvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo240: + li x25, 0xDEADBEA7 + + csrrw x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo242: + li x25, 0xDEADBEA7 + + csrrwi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo244: + li x25, 0xDEADBEA7 + + csrrs x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo246: + li x25, 0xDEADBEA7 + + csrrc x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo248: + li x25, 0xDEADBEA7 + + csrrsi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo250: + li x25, 0xDEADBEA7 + + csrrci x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mtvec_238: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mcounteren_252 + csrw mtvec, x1 + + csrr x23, mcounteren + + j _j_test_s_mcounteren_252 + + _m_trap_from_s_mcounteren_252: + bnez x30, _j_end_s_mcounteren_252 + + csrr x25, mcause + csrr x24, mcounteren + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mcounteren_252: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo252: + li x25, 0xDEADBEA7 + + csrrw x1, mcounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo254: + li x25, 0xDEADBEA7 + + csrrw x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo256: + li x25, 0xDEADBEA7 + + csrrwi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo258: + li x25, 0xDEADBEA7 + + csrrs x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo260: + li x25, 0xDEADBEA7 + + csrrc x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo262: + li x25, 0xDEADBEA7 + + csrrsi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo264: + li x25, 0xDEADBEA7 + + csrrci x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mcounteren_252: + + li x30, 0 + la x1, _m_trap_from_u_mcounteren_266 + csrw mtvec, x1 + + csrr x23, mcounteren + + j _j_test_u_mcounteren_266 + + _m_trap_from_u_mcounteren_266: + bnez x30, _j_end_u_mcounteren_266 + + csrr x25, mcause + csrr x24, mcounteren + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mcounteren_266: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo266: + li x25, 0xDEADBEA7 + + csrrw x1, mcounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo268: + li x25, 0xDEADBEA7 + + csrrw x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo270: + li x25, 0xDEADBEA7 + + csrrwi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo272: + li x25, 0xDEADBEA7 + + csrrs x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo274: + li x25, 0xDEADBEA7 + + csrrc x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo276: + li x25, 0xDEADBEA7 + + csrrsi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo278: + li x25, 0xDEADBEA7 + + csrrci x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mcounteren_266: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mcounteren_280 + csrw mtvec, x1 + + csrr x23, mcounteren + + j _j_test_s_mcounteren_280 + + _m_trap_from_s_mcounteren_280: + bnez x30, _j_end_s_mcounteren_280 + + csrr x25, mcause + csrr x24, mcounteren + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mcounteren_280: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo280: + li x25, 0xDEADBEA7 + + csrrw x1, mcounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo282: + li x25, 0xDEADBEA7 + + csrrw x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo284: + li x25, 0xDEADBEA7 + + csrrwi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo286: + li x25, 0xDEADBEA7 + + csrrs x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo288: + li x25, 0xDEADBEA7 + + csrrc x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo290: + li x25, 0xDEADBEA7 + + csrrsi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo292: + li x25, 0xDEADBEA7 + + csrrci x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mcounteren_280: + + li x30, 0 + la x1, _m_trap_from_u_mcounteren_294 + csrw mtvec, x1 + + csrr x23, mcounteren + + j _j_test_u_mcounteren_294 + + _m_trap_from_u_mcounteren_294: + bnez x30, _j_end_u_mcounteren_294 + + csrr x25, mcause + csrr x24, mcounteren + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mcounteren_294: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo294: + li x25, 0xDEADBEA7 + + csrrw x1, mcounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo296: + li x25, 0xDEADBEA7 + + csrrw x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo298: + li x25, 0xDEADBEA7 + + csrrwi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo300: + li x25, 0xDEADBEA7 + + csrrs x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo302: + li x25, 0xDEADBEA7 + + csrrc x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo304: + li x25, 0xDEADBEA7 + + csrrsi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo306: + li x25, 0xDEADBEA7 + + csrrci x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mcounteren_294: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mscratch_308 + csrw mtvec, x1 + + csrr x23, mscratch + + j _j_test_s_mscratch_308 + + _m_trap_from_s_mscratch_308: + bnez x30, _j_end_s_mscratch_308 + + csrr x25, mcause + csrr x24, mscratch + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mscratch_308: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo308: + li x25, 0xDEADBEA7 + + csrrw x1, mscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo310: + li x25, 0xDEADBEA7 + + csrrw x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo312: + li x25, 0xDEADBEA7 + + csrrwi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo314: + li x25, 0xDEADBEA7 + + csrrs x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo316: + li x25, 0xDEADBEA7 + + csrrc x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo318: + li x25, 0xDEADBEA7 + + csrrsi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo320: + li x25, 0xDEADBEA7 + + csrrci x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mscratch_308: + + li x30, 0 + la x1, _m_trap_from_u_mscratch_322 + csrw mtvec, x1 + + csrr x23, mscratch + + j _j_test_u_mscratch_322 + + _m_trap_from_u_mscratch_322: + bnez x30, _j_end_u_mscratch_322 + + csrr x25, mcause + csrr x24, mscratch + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mscratch_322: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo322: + li x25, 0xDEADBEA7 + + csrrw x1, mscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo324: + li x25, 0xDEADBEA7 + + csrrw x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo326: + li x25, 0xDEADBEA7 + + csrrwi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo328: + li x25, 0xDEADBEA7 + + csrrs x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo330: + li x25, 0xDEADBEA7 + + csrrc x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo332: + li x25, 0xDEADBEA7 + + csrrsi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo334: + li x25, 0xDEADBEA7 + + csrrci x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mscratch_322: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mscratch_336 + csrw mtvec, x1 + + csrr x23, mscratch + + j _j_test_s_mscratch_336 + + _m_trap_from_s_mscratch_336: + bnez x30, _j_end_s_mscratch_336 + + csrr x25, mcause + csrr x24, mscratch + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mscratch_336: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo336: + li x25, 0xDEADBEA7 + + csrrw x1, mscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo338: + li x25, 0xDEADBEA7 + + csrrw x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo340: + li x25, 0xDEADBEA7 + + csrrwi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo342: + li x25, 0xDEADBEA7 + + csrrs x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo344: + li x25, 0xDEADBEA7 + + csrrc x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo346: + li x25, 0xDEADBEA7 + + csrrsi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo348: + li x25, 0xDEADBEA7 + + csrrci x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mscratch_336: + + li x30, 0 + la x1, _m_trap_from_u_mscratch_350 + csrw mtvec, x1 + + csrr x23, mscratch + + j _j_test_u_mscratch_350 + + _m_trap_from_u_mscratch_350: + bnez x30, _j_end_u_mscratch_350 + + csrr x25, mcause + csrr x24, mscratch + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mscratch_350: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo350: + li x25, 0xDEADBEA7 + + csrrw x1, mscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo352: + li x25, 0xDEADBEA7 + + csrrw x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo354: + li x25, 0xDEADBEA7 + + csrrwi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo356: + li x25, 0xDEADBEA7 + + csrrs x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo358: + li x25, 0xDEADBEA7 + + csrrc x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo360: + li x25, 0xDEADBEA7 + + csrrsi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo362: + li x25, 0xDEADBEA7 + + csrrci x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mscratch_350: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mepc_364 + csrw mtvec, x1 + + csrr x23, mepc + + j _j_test_s_mepc_364 + + _m_trap_from_s_mepc_364: + bnez x30, _j_end_s_mepc_364 + + csrr x25, mcause + csrr x24, mepc + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mepc_364: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo364: + li x25, 0xDEADBEA7 + + csrrw x1, mepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo365: + li x25, 0xDEADBEA7 + + csrrw x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo366: + li x25, 0xDEADBEA7 + + csrrwi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo367: + li x25, 0xDEADBEA7 + + csrrs x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo368: + li x25, 0xDEADBEA7 + + csrrc x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo369: + li x25, 0xDEADBEA7 + + csrrsi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo370: + li x25, 0xDEADBEA7 + + csrrci x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mepc_364: + + li x30, 0 + la x1, _m_trap_from_u_mepc_371 + csrw mtvec, x1 + + csrr x23, mepc + + j _j_test_u_mepc_371 + + _m_trap_from_u_mepc_371: + bnez x30, _j_end_u_mepc_371 + + csrr x25, mcause + csrr x24, mepc + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mepc_371: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo371: + li x25, 0xDEADBEA7 + + csrrw x1, mepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo372: + li x25, 0xDEADBEA7 + + csrrw x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo373: + li x25, 0xDEADBEA7 + + csrrwi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo374: + li x25, 0xDEADBEA7 + + csrrs x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo375: + li x25, 0xDEADBEA7 + + csrrc x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo376: + li x25, 0xDEADBEA7 + + csrrsi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo377: + li x25, 0xDEADBEA7 + + csrrci x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mepc_371: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mepc_378 + csrw mtvec, x1 + + csrr x23, mepc + + j _j_test_s_mepc_378 + + _m_trap_from_s_mepc_378: + bnez x30, _j_end_s_mepc_378 + + csrr x25, mcause + csrr x24, mepc + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mepc_378: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo378: + li x25, 0xDEADBEA7 + + csrrw x1, mepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo379: + li x25, 0xDEADBEA7 + + csrrw x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo380: + li x25, 0xDEADBEA7 + + csrrwi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo381: + li x25, 0xDEADBEA7 + + csrrs x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo382: + li x25, 0xDEADBEA7 + + csrrc x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo383: + li x25, 0xDEADBEA7 + + csrrsi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo384: + li x25, 0xDEADBEA7 + + csrrci x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mepc_378: + + li x30, 0 + la x1, _m_trap_from_u_mepc_385 + csrw mtvec, x1 + + csrr x23, mepc + + j _j_test_u_mepc_385 + + _m_trap_from_u_mepc_385: + bnez x30, _j_end_u_mepc_385 + + csrr x25, mcause + csrr x24, mepc + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mepc_385: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo385: + li x25, 0xDEADBEA7 + + csrrw x1, mepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo386: + li x25, 0xDEADBEA7 + + csrrw x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo387: + li x25, 0xDEADBEA7 + + csrrwi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo388: + li x25, 0xDEADBEA7 + + csrrs x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo389: + li x25, 0xDEADBEA7 + + csrrc x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo390: + li x25, 0xDEADBEA7 + + csrrsi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo391: + li x25, 0xDEADBEA7 + + csrrci x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mepc_385: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mcause_392 + csrw mtvec, x1 + + csrr x23, mcause + + j _j_test_s_mcause_392 + + _m_trap_from_s_mcause_392: + bnez x30, _j_end_s_mcause_392 + + csrr x25, mcause + csrr x24, mcause + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mcause_392: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo392: + li x25, 0xDEADBEA7 + + csrrw x1, mcause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo393: + li x25, 0xDEADBEA7 + + csrrw x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo394: + li x25, 0xDEADBEA7 + + csrrwi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo395: + li x25, 0xDEADBEA7 + + csrrs x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo396: + li x25, 0xDEADBEA7 + + csrrc x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo397: + li x25, 0xDEADBEA7 + + csrrsi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo398: + li x25, 0xDEADBEA7 + + csrrci x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mcause_392: + + li x30, 0 + la x1, _m_trap_from_u_mcause_399 + csrw mtvec, x1 + + csrr x23, mcause + + j _j_test_u_mcause_399 + + _m_trap_from_u_mcause_399: + bnez x30, _j_end_u_mcause_399 + + csrr x25, mcause + csrr x24, mcause + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mcause_399: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo399: + li x25, 0xDEADBEA7 + + csrrw x1, mcause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo400: + li x25, 0xDEADBEA7 + + csrrw x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo401: + li x25, 0xDEADBEA7 + + csrrwi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo402: + li x25, 0xDEADBEA7 + + csrrs x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo403: + li x25, 0xDEADBEA7 + + csrrc x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo404: + li x25, 0xDEADBEA7 + + csrrsi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo405: + li x25, 0xDEADBEA7 + + csrrci x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mcause_399: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mcause_406 + csrw mtvec, x1 + + csrr x23, mcause + + j _j_test_s_mcause_406 + + _m_trap_from_s_mcause_406: + bnez x30, _j_end_s_mcause_406 + + csrr x25, mcause + csrr x24, mcause + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mcause_406: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo406: + li x25, 0xDEADBEA7 + + csrrw x1, mcause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo407: + li x25, 0xDEADBEA7 + + csrrw x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo408: + li x25, 0xDEADBEA7 + + csrrwi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo409: + li x25, 0xDEADBEA7 + + csrrs x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo410: + li x25, 0xDEADBEA7 + + csrrc x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo411: + li x25, 0xDEADBEA7 + + csrrsi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo412: + li x25, 0xDEADBEA7 + + csrrci x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mcause_406: + + li x30, 0 + la x1, _m_trap_from_u_mcause_413 + csrw mtvec, x1 + + csrr x23, mcause + + j _j_test_u_mcause_413 + + _m_trap_from_u_mcause_413: + bnez x30, _j_end_u_mcause_413 + + csrr x25, mcause + csrr x24, mcause + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mcause_413: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo413: + li x25, 0xDEADBEA7 + + csrrw x1, mcause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo414: + li x25, 0xDEADBEA7 + + csrrw x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo415: + li x25, 0xDEADBEA7 + + csrrwi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo416: + li x25, 0xDEADBEA7 + + csrrs x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo417: + li x25, 0xDEADBEA7 + + csrrc x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo418: + li x25, 0xDEADBEA7 + + csrrsi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo419: + li x25, 0xDEADBEA7 + + csrrci x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mcause_413: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mtval_420 + csrw mtvec, x1 + + csrr x23, mtval + + j _j_test_s_mtval_420 + + _m_trap_from_s_mtval_420: + bnez x30, _j_end_s_mtval_420 + + csrr x25, mcause + csrr x24, mtval + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mtval_420: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo420: + li x25, 0xDEADBEA7 + + csrrw x1, mtval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo421: + li x25, 0xDEADBEA7 + + csrrw x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo422: + li x25, 0xDEADBEA7 + + csrrwi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo423: + li x25, 0xDEADBEA7 + + csrrs x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo424: + li x25, 0xDEADBEA7 + + csrrc x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo425: + li x25, 0xDEADBEA7 + + csrrsi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo426: + li x25, 0xDEADBEA7 + + csrrci x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mtval_420: + + li x30, 0 + la x1, _m_trap_from_u_mtval_427 + csrw mtvec, x1 + + csrr x23, mtval + + j _j_test_u_mtval_427 + + _m_trap_from_u_mtval_427: + bnez x30, _j_end_u_mtval_427 + + csrr x25, mcause + csrr x24, mtval + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mtval_427: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo427: + li x25, 0xDEADBEA7 + + csrrw x1, mtval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo428: + li x25, 0xDEADBEA7 + + csrrw x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo429: + li x25, 0xDEADBEA7 + + csrrwi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo430: + li x25, 0xDEADBEA7 + + csrrs x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo431: + li x25, 0xDEADBEA7 + + csrrc x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo432: + li x25, 0xDEADBEA7 + + csrrsi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo433: + li x25, 0xDEADBEA7 + + csrrci x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mtval_427: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mtval_434 + csrw mtvec, x1 + + csrr x23, mtval + + j _j_test_s_mtval_434 + + _m_trap_from_s_mtval_434: + bnez x30, _j_end_s_mtval_434 + + csrr x25, mcause + csrr x24, mtval + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mtval_434: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo434: + li x25, 0xDEADBEA7 + + csrrw x1, mtval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo435: + li x25, 0xDEADBEA7 + + csrrw x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo436: + li x25, 0xDEADBEA7 + + csrrwi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo437: + li x25, 0xDEADBEA7 + + csrrs x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo438: + li x25, 0xDEADBEA7 + + csrrc x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo439: + li x25, 0xDEADBEA7 + + csrrsi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo440: + li x25, 0xDEADBEA7 + + csrrci x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mtval_434: + + li x30, 0 + la x1, _m_trap_from_u_mtval_441 + csrw mtvec, x1 + + csrr x23, mtval + + j _j_test_u_mtval_441 + + _m_trap_from_u_mtval_441: + bnez x30, _j_end_u_mtval_441 + + csrr x25, mcause + csrr x24, mtval + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mtval_441: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo441: + li x25, 0xDEADBEA7 + + csrrw x1, mtval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo442: + li x25, 0xDEADBEA7 + + csrrw x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo443: + li x25, 0xDEADBEA7 + + csrrwi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo444: + li x25, 0xDEADBEA7 + + csrrs x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo445: + li x25, 0xDEADBEA7 + + csrrc x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo446: + li x25, 0xDEADBEA7 + + csrrsi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo447: + li x25, 0xDEADBEA7 + + csrrci x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mtval_441: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mip_448 + csrw mtvec, x1 + + csrr x23, mip + + j _j_test_s_mip_448 + + _m_trap_from_s_mip_448: + bnez x30, _j_end_s_mip_448 + + csrr x25, mcause + csrr x24, mip + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mip_448: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo448: + li x25, 0xDEADBEA7 + + csrrw x1, mip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo450: + li x25, 0xDEADBEA7 + + csrrw x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo452: + li x25, 0xDEADBEA7 + + csrrwi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo454: + li x25, 0xDEADBEA7 + + csrrs x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo456: + li x25, 0xDEADBEA7 + + csrrc x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo458: + li x25, 0xDEADBEA7 + + csrrsi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo460: + li x25, 0xDEADBEA7 + + csrrci x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mip_448: + + li x30, 0 + la x1, _m_trap_from_u_mip_462 + csrw mtvec, x1 + + csrr x23, mip + + j _j_test_u_mip_462 + + _m_trap_from_u_mip_462: + bnez x30, _j_end_u_mip_462 + + csrr x25, mcause + csrr x24, mip + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mip_462: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo462: + li x25, 0xDEADBEA7 + + csrrw x1, mip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo464: + li x25, 0xDEADBEA7 + + csrrw x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo466: + li x25, 0xDEADBEA7 + + csrrwi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo468: + li x25, 0xDEADBEA7 + + csrrs x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo470: + li x25, 0xDEADBEA7 + + csrrc x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo472: + li x25, 0xDEADBEA7 + + csrrsi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo474: + li x25, 0xDEADBEA7 + + csrrci x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mip_462: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mip_476 + csrw mtvec, x1 + + csrr x23, mip + + j _j_test_s_mip_476 + + _m_trap_from_s_mip_476: + bnez x30, _j_end_s_mip_476 + + csrr x25, mcause + csrr x24, mip + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mip_476: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo476: + li x25, 0xDEADBEA7 + + csrrw x1, mip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo478: + li x25, 0xDEADBEA7 + + csrrw x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo480: + li x25, 0xDEADBEA7 + + csrrwi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo482: + li x25, 0xDEADBEA7 + + csrrs x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo484: + li x25, 0xDEADBEA7 + + csrrc x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo486: + li x25, 0xDEADBEA7 + + csrrsi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo488: + li x25, 0xDEADBEA7 + + csrrci x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mip_476: + + li x30, 0 + la x1, _m_trap_from_u_mip_490 + csrw mtvec, x1 + + csrr x23, mip + + j _j_test_u_mip_490 + + _m_trap_from_u_mip_490: + bnez x30, _j_end_u_mip_490 + + csrr x25, mcause + csrr x24, mip + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mip_490: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo490: + li x25, 0xDEADBEA7 + + csrrw x1, mip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo492: + li x25, 0xDEADBEA7 + + csrrw x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo494: + li x25, 0xDEADBEA7 + + csrrwi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo496: + li x25, 0xDEADBEA7 + + csrrs x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo498: + li x25, 0xDEADBEA7 + + csrrc x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo500: + li x25, 0xDEADBEA7 + + csrrsi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo502: + li x25, 0xDEADBEA7 + + csrrci x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mip_490: + + csrw mtvec, x19 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 504, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S new file mode 100644 index 00000000..c176e619 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S @@ -0,0 +1,2627 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-CSR-PERMISSIONS-S.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:21.731076// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sstatus_0 + csrw mtvec, x1 + + csrr x23, sstatus + + j _j_test_u_sstatus_0 + + _m_trap_from_u_sstatus_0: + bnez x30, _j_end_u_sstatus_0 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sstatus_0: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo0: + li x25, 0xDEADBEA7 + + csrrw x1, sstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo1: + li x25, 0xDEADBEA7 + + csrrw x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo2: + li x25, 0xDEADBEA7 + + csrrwi x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo3: + li x25, 0xDEADBEA7 + + csrrs x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo4: + li x25, 0xDEADBEA7 + + csrrc x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo5: + li x25, 0xDEADBEA7 + + csrrsi x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo6: + li x25, 0xDEADBEA7 + + csrrci x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sstatus_0: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sstatus_7 + csrw mtvec, x1 + + csrr x23, sstatus + + j _j_test_u_sstatus_7 + + _m_trap_from_u_sstatus_7: + bnez x30, _j_end_u_sstatus_7 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sstatus_7: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo7: + li x25, 0xDEADBEA7 + + csrrw x1, sstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo8: + li x25, 0xDEADBEA7 + + csrrw x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo9: + li x25, 0xDEADBEA7 + + csrrwi x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo10: + li x25, 0xDEADBEA7 + + csrrs x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo11: + li x25, 0xDEADBEA7 + + csrrc x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo12: + li x25, 0xDEADBEA7 + + csrrsi x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo13: + li x25, 0xDEADBEA7 + + csrrci x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sstatus_7: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sedeleg_14 + csrw mtvec, x1 + + csrr x23, sedeleg + + j _j_test_u_sedeleg_14 + + _m_trap_from_u_sedeleg_14: + bnez x30, _j_end_u_sedeleg_14 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sedeleg_14: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo14: + li x25, 0xDEADBEA7 + + csrrw x1, sedeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo15: + li x25, 0xDEADBEA7 + + csrrw x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo16: + li x25, 0xDEADBEA7 + + csrrwi x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo17: + li x25, 0xDEADBEA7 + + csrrs x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo18: + li x25, 0xDEADBEA7 + + csrrc x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo19: + li x25, 0xDEADBEA7 + + csrrsi x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo20: + li x25, 0xDEADBEA7 + + csrrci x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sedeleg_14: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sedeleg_21 + csrw mtvec, x1 + + csrr x23, sedeleg + + j _j_test_u_sedeleg_21 + + _m_trap_from_u_sedeleg_21: + bnez x30, _j_end_u_sedeleg_21 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sedeleg_21: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo21: + li x25, 0xDEADBEA7 + + csrrw x1, sedeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo22: + li x25, 0xDEADBEA7 + + csrrw x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo23: + li x25, 0xDEADBEA7 + + csrrwi x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo24: + li x25, 0xDEADBEA7 + + csrrs x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo25: + li x25, 0xDEADBEA7 + + csrrc x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo26: + li x25, 0xDEADBEA7 + + csrrsi x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo27: + li x25, 0xDEADBEA7 + + csrrci x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sedeleg_21: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sideleg_28 + csrw mtvec, x1 + + csrr x23, sideleg + + j _j_test_u_sideleg_28 + + _m_trap_from_u_sideleg_28: + bnez x30, _j_end_u_sideleg_28 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sideleg_28: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo28: + li x25, 0xDEADBEA7 + + csrrw x1, sideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo29: + li x25, 0xDEADBEA7 + + csrrw x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo30: + li x25, 0xDEADBEA7 + + csrrwi x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo31: + li x25, 0xDEADBEA7 + + csrrs x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo32: + li x25, 0xDEADBEA7 + + csrrc x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo33: + li x25, 0xDEADBEA7 + + csrrsi x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo34: + li x25, 0xDEADBEA7 + + csrrci x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sideleg_28: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sideleg_35 + csrw mtvec, x1 + + csrr x23, sideleg + + j _j_test_u_sideleg_35 + + _m_trap_from_u_sideleg_35: + bnez x30, _j_end_u_sideleg_35 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sideleg_35: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo35: + li x25, 0xDEADBEA7 + + csrrw x1, sideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo36: + li x25, 0xDEADBEA7 + + csrrw x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo37: + li x25, 0xDEADBEA7 + + csrrwi x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo38: + li x25, 0xDEADBEA7 + + csrrs x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo39: + li x25, 0xDEADBEA7 + + csrrc x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo40: + li x25, 0xDEADBEA7 + + csrrsi x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo41: + li x25, 0xDEADBEA7 + + csrrci x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sideleg_35: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sie_42 + csrw mtvec, x1 + + csrr x23, sie + + j _j_test_u_sie_42 + + _m_trap_from_u_sie_42: + bnez x30, _j_end_u_sie_42 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sie_42: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo42: + li x25, 0xDEADBEA7 + + csrrw x1, sie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo43: + li x25, 0xDEADBEA7 + + csrrw x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo44: + li x25, 0xDEADBEA7 + + csrrwi x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo45: + li x25, 0xDEADBEA7 + + csrrs x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo46: + li x25, 0xDEADBEA7 + + csrrc x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo47: + li x25, 0xDEADBEA7 + + csrrsi x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo48: + li x25, 0xDEADBEA7 + + csrrci x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sie_42: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sie_49 + csrw mtvec, x1 + + csrr x23, sie + + j _j_test_u_sie_49 + + _m_trap_from_u_sie_49: + bnez x30, _j_end_u_sie_49 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sie_49: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo49: + li x25, 0xDEADBEA7 + + csrrw x1, sie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo50: + li x25, 0xDEADBEA7 + + csrrw x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo51: + li x25, 0xDEADBEA7 + + csrrwi x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo52: + li x25, 0xDEADBEA7 + + csrrs x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo53: + li x25, 0xDEADBEA7 + + csrrc x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo54: + li x25, 0xDEADBEA7 + + csrrsi x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo55: + li x25, 0xDEADBEA7 + + csrrci x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sie_49: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_stvec_56 + csrw mtvec, x1 + + csrr x23, stvec + + j _j_test_u_stvec_56 + + _m_trap_from_u_stvec_56: + bnez x30, _j_end_u_stvec_56 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_stvec_56: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo56: + li x25, 0xDEADBEA7 + + csrrw x1, stvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo57: + li x25, 0xDEADBEA7 + + csrrw x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo58: + li x25, 0xDEADBEA7 + + csrrwi x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo59: + li x25, 0xDEADBEA7 + + csrrs x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo60: + li x25, 0xDEADBEA7 + + csrrc x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo61: + li x25, 0xDEADBEA7 + + csrrsi x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo62: + li x25, 0xDEADBEA7 + + csrrci x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_stvec_56: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_stvec_63 + csrw mtvec, x1 + + csrr x23, stvec + + j _j_test_u_stvec_63 + + _m_trap_from_u_stvec_63: + bnez x30, _j_end_u_stvec_63 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_stvec_63: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo63: + li x25, 0xDEADBEA7 + + csrrw x1, stvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo64: + li x25, 0xDEADBEA7 + + csrrw x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo65: + li x25, 0xDEADBEA7 + + csrrwi x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo66: + li x25, 0xDEADBEA7 + + csrrs x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo67: + li x25, 0xDEADBEA7 + + csrrc x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo68: + li x25, 0xDEADBEA7 + + csrrsi x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo69: + li x25, 0xDEADBEA7 + + csrrci x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_stvec_63: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_scounteren_70 + csrw mtvec, x1 + + csrr x23, scounteren + + j _j_test_u_scounteren_70 + + _m_trap_from_u_scounteren_70: + bnez x30, _j_end_u_scounteren_70 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_scounteren_70: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo70: + li x25, 0xDEADBEA7 + + csrrw x1, scounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo71: + li x25, 0xDEADBEA7 + + csrrw x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo72: + li x25, 0xDEADBEA7 + + csrrwi x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo73: + li x25, 0xDEADBEA7 + + csrrs x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo74: + li x25, 0xDEADBEA7 + + csrrc x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo75: + li x25, 0xDEADBEA7 + + csrrsi x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo76: + li x25, 0xDEADBEA7 + + csrrci x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_scounteren_70: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_scounteren_77 + csrw mtvec, x1 + + csrr x23, scounteren + + j _j_test_u_scounteren_77 + + _m_trap_from_u_scounteren_77: + bnez x30, _j_end_u_scounteren_77 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_scounteren_77: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo77: + li x25, 0xDEADBEA7 + + csrrw x1, scounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo78: + li x25, 0xDEADBEA7 + + csrrw x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo79: + li x25, 0xDEADBEA7 + + csrrwi x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo80: + li x25, 0xDEADBEA7 + + csrrs x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo81: + li x25, 0xDEADBEA7 + + csrrc x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo82: + li x25, 0xDEADBEA7 + + csrrsi x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo83: + li x25, 0xDEADBEA7 + + csrrci x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_scounteren_77: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sscratch_84 + csrw mtvec, x1 + + csrr x23, sscratch + + j _j_test_u_sscratch_84 + + _m_trap_from_u_sscratch_84: + bnez x30, _j_end_u_sscratch_84 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sscratch_84: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo84: + li x25, 0xDEADBEA7 + + csrrw x1, sscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo85: + li x25, 0xDEADBEA7 + + csrrw x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo86: + li x25, 0xDEADBEA7 + + csrrwi x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo87: + li x25, 0xDEADBEA7 + + csrrs x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo88: + li x25, 0xDEADBEA7 + + csrrc x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo89: + li x25, 0xDEADBEA7 + + csrrsi x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo90: + li x25, 0xDEADBEA7 + + csrrci x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sscratch_84: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sscratch_91 + csrw mtvec, x1 + + csrr x23, sscratch + + j _j_test_u_sscratch_91 + + _m_trap_from_u_sscratch_91: + bnez x30, _j_end_u_sscratch_91 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sscratch_91: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo91: + li x25, 0xDEADBEA7 + + csrrw x1, sscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo92: + li x25, 0xDEADBEA7 + + csrrw x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo93: + li x25, 0xDEADBEA7 + + csrrwi x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo94: + li x25, 0xDEADBEA7 + + csrrs x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo95: + li x25, 0xDEADBEA7 + + csrrc x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo96: + li x25, 0xDEADBEA7 + + csrrsi x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo97: + li x25, 0xDEADBEA7 + + csrrci x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sscratch_91: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sepc_98 + csrw mtvec, x1 + + csrr x23, sepc + + j _j_test_u_sepc_98 + + _m_trap_from_u_sepc_98: + bnez x30, _j_end_u_sepc_98 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sepc_98: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo98: + li x25, 0xDEADBEA7 + + csrrw x1, sepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo99: + li x25, 0xDEADBEA7 + + csrrw x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo100: + li x25, 0xDEADBEA7 + + csrrwi x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo101: + li x25, 0xDEADBEA7 + + csrrs x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo102: + li x25, 0xDEADBEA7 + + csrrc x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo103: + li x25, 0xDEADBEA7 + + csrrsi x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo104: + li x25, 0xDEADBEA7 + + csrrci x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sepc_98: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sepc_105 + csrw mtvec, x1 + + csrr x23, sepc + + j _j_test_u_sepc_105 + + _m_trap_from_u_sepc_105: + bnez x30, _j_end_u_sepc_105 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sepc_105: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo105: + li x25, 0xDEADBEA7 + + csrrw x1, sepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo106: + li x25, 0xDEADBEA7 + + csrrw x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo107: + li x25, 0xDEADBEA7 + + csrrwi x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo108: + li x25, 0xDEADBEA7 + + csrrs x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo109: + li x25, 0xDEADBEA7 + + csrrc x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo110: + li x25, 0xDEADBEA7 + + csrrsi x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo111: + li x25, 0xDEADBEA7 + + csrrci x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sepc_105: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_scause_112 + csrw mtvec, x1 + + csrr x23, scause + + j _j_test_u_scause_112 + + _m_trap_from_u_scause_112: + bnez x30, _j_end_u_scause_112 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_scause_112: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo112: + li x25, 0xDEADBEA7 + + csrrw x1, scause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo113: + li x25, 0xDEADBEA7 + + csrrw x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo114: + li x25, 0xDEADBEA7 + + csrrwi x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo115: + li x25, 0xDEADBEA7 + + csrrs x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo116: + li x25, 0xDEADBEA7 + + csrrc x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo117: + li x25, 0xDEADBEA7 + + csrrsi x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo118: + li x25, 0xDEADBEA7 + + csrrci x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_scause_112: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_scause_119 + csrw mtvec, x1 + + csrr x23, scause + + j _j_test_u_scause_119 + + _m_trap_from_u_scause_119: + bnez x30, _j_end_u_scause_119 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_scause_119: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo119: + li x25, 0xDEADBEA7 + + csrrw x1, scause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo120: + li x25, 0xDEADBEA7 + + csrrw x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo121: + li x25, 0xDEADBEA7 + + csrrwi x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo122: + li x25, 0xDEADBEA7 + + csrrs x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo123: + li x25, 0xDEADBEA7 + + csrrc x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo124: + li x25, 0xDEADBEA7 + + csrrsi x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo125: + li x25, 0xDEADBEA7 + + csrrci x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_scause_119: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_stval_126 + csrw mtvec, x1 + + csrr x23, stval + + j _j_test_u_stval_126 + + _m_trap_from_u_stval_126: + bnez x30, _j_end_u_stval_126 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_stval_126: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo126: + li x25, 0xDEADBEA7 + + csrrw x1, stval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo127: + li x25, 0xDEADBEA7 + + csrrw x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo128: + li x25, 0xDEADBEA7 + + csrrwi x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo129: + li x25, 0xDEADBEA7 + + csrrs x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo130: + li x25, 0xDEADBEA7 + + csrrc x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo131: + li x25, 0xDEADBEA7 + + csrrsi x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo132: + li x25, 0xDEADBEA7 + + csrrci x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_stval_126: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_stval_133 + csrw mtvec, x1 + + csrr x23, stval + + j _j_test_u_stval_133 + + _m_trap_from_u_stval_133: + bnez x30, _j_end_u_stval_133 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_stval_133: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo133: + li x25, 0xDEADBEA7 + + csrrw x1, stval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo134: + li x25, 0xDEADBEA7 + + csrrw x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo135: + li x25, 0xDEADBEA7 + + csrrwi x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo136: + li x25, 0xDEADBEA7 + + csrrs x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo137: + li x25, 0xDEADBEA7 + + csrrc x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo138: + li x25, 0xDEADBEA7 + + csrrsi x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo139: + li x25, 0xDEADBEA7 + + csrrci x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_stval_133: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sip_140 + csrw mtvec, x1 + + csrr x23, sip + + j _j_test_u_sip_140 + + _m_trap_from_u_sip_140: + bnez x30, _j_end_u_sip_140 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sip_140: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo140: + li x25, 0xDEADBEA7 + + csrrw x1, sip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo141: + li x25, 0xDEADBEA7 + + csrrw x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo142: + li x25, 0xDEADBEA7 + + csrrwi x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo143: + li x25, 0xDEADBEA7 + + csrrs x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo144: + li x25, 0xDEADBEA7 + + csrrc x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo145: + li x25, 0xDEADBEA7 + + csrrsi x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo146: + li x25, 0xDEADBEA7 + + csrrci x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sip_140: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sip_147 + csrw mtvec, x1 + + csrr x23, sip + + j _j_test_u_sip_147 + + _m_trap_from_u_sip_147: + bnez x30, _j_end_u_sip_147 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sip_147: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo147: + li x25, 0xDEADBEA7 + + csrrw x1, sip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo148: + li x25, 0xDEADBEA7 + + csrrw x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo149: + li x25, 0xDEADBEA7 + + csrrwi x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo150: + li x25, 0xDEADBEA7 + + csrrs x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo151: + li x25, 0xDEADBEA7 + + csrrc x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo152: + li x25, 0xDEADBEA7 + + csrrsi x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo153: + li x25, 0xDEADBEA7 + + csrrci x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sip_147: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_satp_154 + csrw mtvec, x1 + + csrr x23, satp + + j _j_test_u_satp_154 + + _m_trap_from_u_satp_154: + bnez x30, _j_end_u_satp_154 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_satp_154: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo154: + li x25, 0xDEADBEA7 + + csrrw x1, satp, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo155: + li x25, 0xDEADBEA7 + + csrrw x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo156: + li x25, 0xDEADBEA7 + + csrrwi x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo157: + li x25, 0xDEADBEA7 + + csrrs x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo158: + li x25, 0xDEADBEA7 + + csrrc x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo159: + li x25, 0xDEADBEA7 + + csrrsi x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo160: + li x25, 0xDEADBEA7 + + csrrci x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_satp_154: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_satp_161 + csrw mtvec, x1 + + csrr x23, satp + + j _j_test_u_satp_161 + + _m_trap_from_u_satp_161: + bnez x30, _j_end_u_satp_161 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_satp_161: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo161: + li x25, 0xDEADBEA7 + + csrrw x1, satp, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo162: + li x25, 0xDEADBEA7 + + csrrw x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo163: + li x25, 0xDEADBEA7 + + csrrwi x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo164: + li x25, 0xDEADBEA7 + + csrrs x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo165: + li x25, 0xDEADBEA7 + + csrrc x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo166: + li x25, 0xDEADBEA7 + + csrrsi x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo167: + li x25, 0xDEADBEA7 + + csrrci x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_satp_161: + + csrw mtvec, x19 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 168, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S new file mode 100644 index 00000000..0b4701d1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S @@ -0,0 +1,3778 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MARCHID.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:52.352985// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + # Testcase 0 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest0 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest0: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend0: + + csrrw x0, mtvec, x31 + sd x25, 0(x6) +sd x15, 8(x6) + + # Testcase 2 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest2 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest2: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 0 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend2: + + csrrw x0, mtvec, x31 + sd x25, 16(x6) +sd x15, 24(x6) + + # Testcase 4 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest4 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest4: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend4: + + csrrw x0, mtvec, x31 + sd x25, 32(x6) +sd x15, 40(x6) + + # Testcase 6 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest6 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest6: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 1 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend6: + + csrrw x0, mtvec, x31 + sd x25, 48(x6) +sd x15, 56(x6) + + # Testcase 8 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest8 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest8: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend8: + + csrrw x0, mtvec, x31 + sd x25, 64(x6) +sd x15, 72(x6) + + # Testcase 10 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest10 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest10: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend10: + + csrrw x0, mtvec, x31 + sd x25, 80(x6) +sd x15, 88(x6) + + # Testcase 12 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest12 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest12: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend12: + + csrrw x0, mtvec, x31 + sd x25, 96(x6) +sd x15, 104(x6) + + # Testcase 14 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest14 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest14: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrci x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend14: + + csrrw x0, mtvec, x31 + sd x25, 112(x6) +sd x15, 120(x6) + + # Testcase 16 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest16 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest16: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend16: + + csrrw x0, mtvec, x31 + sd x25, 128(x6) +sd x15, 136(x6) + + # Testcase 18 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest18 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest18: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend18: + + csrrw x0, mtvec, x31 + sd x25, 144(x6) +sd x15, 152(x6) + + # Testcase 20 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest20 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest20: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend20: + + csrrw x0, mtvec, x31 + sd x25, 160(x6) +sd x15, 168(x6) + + # Testcase 22 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest22 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest22: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend22: + + csrrw x0, mtvec, x31 + sd x25, 176(x6) +sd x15, 184(x6) + + # Testcase 24 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest24 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest24: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 3 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend24: + + csrrw x0, mtvec, x31 + sd x25, 192(x6) +sd x15, 200(x6) + + # Testcase 26 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest26 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest26: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrci x0, marchid, 3 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend26: + + csrrw x0, mtvec, x31 + sd x25, 208(x6) +sd x15, 216(x6) + + # Testcase 28 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest28 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest28: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend28: + + csrrw x0, mtvec, x31 + sd x25, 224(x6) +sd x15, 232(x6) + + # Testcase 30 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest30 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest30: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 31 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend30: + + csrrw x0, mtvec, x31 + sd x25, 240(x6) +sd x15, 248(x6) + + # Testcase 32 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest32 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest32: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend32: + + csrrw x0, mtvec, x31 + sd x25, 256(x6) +sd x15, 264(x6) + + # Testcase 34 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest34 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest34: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend34: + + csrrw x0, mtvec, x31 + sd x25, 272(x6) +sd x15, 280(x6) + + # Testcase 36 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest36 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest36: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 1 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend36: + + csrrw x0, mtvec, x31 + sd x25, 288(x6) +sd x15, 296(x6) + + # Testcase 38 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest38 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest38: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrci x0, marchid, 1 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend38: + + csrrw x0, mtvec, x31 + sd x25, 304(x6) +sd x15, 312(x6) + + # Testcase 40 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest40 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest40: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend40: + + csrrw x0, mtvec, x31 + sd x25, 320(x6) +sd x15, 328(x6) + + # Testcase 42 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest42 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest42: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 0 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend42: + + csrrw x0, mtvec, x31 + sd x25, 336(x6) +sd x15, 344(x6) + + # Testcase 44 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest44 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest44: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend44: + + csrrw x0, mtvec, x31 + sd x25, 352(x6) +sd x15, 360(x6) + + # Testcase 46 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest46 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest46: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend46: + + csrrw x0, mtvec, x31 + sd x25, 368(x6) +sd x15, 376(x6) + + # Testcase 48 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest48 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest48: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend48: + + csrrw x0, mtvec, x31 + sd x25, 384(x6) +sd x15, 392(x6) + + # Testcase 50 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest50 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest50: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrci x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend50: + + csrrw x0, mtvec, x31 + sd x25, 400(x6) +sd x15, 408(x6) + + # Testcase 52 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest52 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest52: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend52: + + csrrw x0, mtvec, x31 + sd x25, 416(x6) +sd x15, 424(x6) + + # Testcase 54 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest54 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest54: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 20 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend54: + + csrrw x0, mtvec, x31 + sd x25, 432(x6) +sd x15, 440(x6) + + # Testcase 56 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest56 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest56: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend56: + + csrrw x0, mtvec, x31 + sd x25, 448(x6) +sd x15, 456(x6) + + # Testcase 58 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest58 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest58: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend58: + + csrrw x0, mtvec, x31 + sd x25, 464(x6) +sd x15, 472(x6) + + # Testcase 60 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest60 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest60: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 28 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend60: + + csrrw x0, mtvec, x31 + sd x25, 480(x6) +sd x15, 488(x6) + + # Testcase 62 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest62 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest62: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrci x0, marchid, 28 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend62: + + csrrw x0, mtvec, x31 + sd x25, 496(x6) +sd x15, 504(x6) + + # Testcase 64 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest64 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest64: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend64: + + csrrw x0, mtvec, x31 + sd x25, 512(x6) +sd x15, 520(x6) + + # Testcase 66 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest66 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest66: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend66: + + csrrw x0, mtvec, x31 + sd x25, 528(x6) +sd x15, 536(x6) + + # Testcase 68 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest68 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest68: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend68: + + csrrw x0, mtvec, x31 + sd x25, 544(x6) +sd x15, 552(x6) + + # Testcase 70 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest70 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest70: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend70: + + csrrw x0, mtvec, x31 + sd x25, 560(x6) +sd x15, 568(x6) + + # Testcase 72 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest72 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest72: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 7 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend72: + + csrrw x0, mtvec, x31 + sd x25, 576(x6) +sd x15, 584(x6) + + # Testcase 74 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest74 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest74: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrci x0, marchid, 7 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend74: + + csrrw x0, mtvec, x31 + sd x25, 592(x6) +sd x15, 600(x6) + + # Testcase 76 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest76 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest76: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend76: + + csrrw x0, mtvec, x31 + sd x25, 608(x6) +sd x15, 616(x6) + + # Testcase 78 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest78 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest78: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 31 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend78: + + csrrw x0, mtvec, x31 + sd x25, 624(x6) +sd x15, 632(x6) + + # Testcase 80 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest80 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest80: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend80: + + csrrw x0, mtvec, x31 + sd x25, 640(x6) +sd x15, 648(x6) + + # Testcase 82 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest82 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest82: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend82: + + csrrw x0, mtvec, x31 + sd x25, 656(x6) +sd x15, 664(x6) + + # Testcase 84 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest84 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest84: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 8 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend84: + + csrrw x0, mtvec, x31 + sd x25, 672(x6) +sd x15, 680(x6) + + # Testcase 86 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest86 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest86: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrci x0, marchid, 8 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend86: + + csrrw x0, mtvec, x31 + sd x25, 688(x6) +sd x15, 696(x6) + + # Testcase 88 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest88 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest88: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend88: + + csrrw x0, mtvec, x31 + sd x25, 704(x6) +sd x15, 712(x6) + + # Testcase 90 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest90 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest90: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 0 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend90: + + csrrw x0, mtvec, x31 + sd x25, 720(x6) +sd x15, 728(x6) + + # Testcase 92 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest92 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest92: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend92: + + csrrw x0, mtvec, x31 + sd x25, 736(x6) +sd x15, 744(x6) + + # Testcase 94 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest94 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest94: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend94: + + csrrw x0, mtvec, x31 + sd x25, 752(x6) +sd x15, 760(x6) + + # Testcase 96 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest96 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest96: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 9 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend96: + + csrrw x0, mtvec, x31 + sd x25, 768(x6) +sd x15, 776(x6) + + # Testcase 98 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest98 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest98: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrci x0, marchid, 9 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend98: + + csrrw x0, mtvec, x31 + sd x25, 784(x6) +sd x15, 792(x6) + + # Testcase 100 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest100 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest100: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend100: + + csrrw x0, mtvec, x31 + sd x25, 800(x6) +sd x15, 808(x6) + + # Testcase 102 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest102 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest102: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 1 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend102: + + csrrw x0, mtvec, x31 + sd x25, 816(x6) +sd x15, 824(x6) + + # Testcase 104 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest104 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest104: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend104: + + csrrw x0, mtvec, x31 + sd x25, 832(x6) +sd x15, 840(x6) + + # Testcase 106 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest106 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest106: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend106: + + csrrw x0, mtvec, x31 + sd x25, 848(x6) +sd x15, 856(x6) + + # Testcase 108 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest108 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest108: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 10 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend108: + + csrrw x0, mtvec, x31 + sd x25, 864(x6) +sd x15, 872(x6) + + # Testcase 110 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest110 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest110: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrci x0, marchid, 10 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend110: + + csrrw x0, mtvec, x31 + sd x25, 880(x6) +sd x15, 888(x6) + + # Testcase 112 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest112 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest112: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend112: + + csrrw x0, mtvec, x31 + sd x25, 896(x6) +sd x15, 904(x6) + + # Testcase 114 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest114 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest114: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend114: + + csrrw x0, mtvec, x31 + sd x25, 912(x6) +sd x15, 920(x6) + + # Testcase 116 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest116 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest116: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend116: + + csrrw x0, mtvec, x31 + sd x25, 928(x6) +sd x15, 936(x6) + + # Testcase 118 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest118 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest118: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend118: + + csrrw x0, mtvec, x31 + sd x25, 944(x6) +sd x15, 952(x6) + + # Testcase 120 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest120 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest120: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 20 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend120: + + csrrw x0, mtvec, x31 + sd x25, 960(x6) +sd x15, 968(x6) + + # Testcase 122 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest122 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest122: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrci x0, marchid, 20 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend122: + + csrrw x0, mtvec, x31 + sd x25, 976(x6) +sd x15, 984(x6) + + # Testcase 124 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest124 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest124: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend124: + + csrrw x0, mtvec, x31 + sd x25, 992(x6) +sd x15, 1000(x6) + + # Testcase 126 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest126 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest126: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend126: + + csrrw x0, mtvec, x31 + sd x25, 1008(x6) +sd x15, 1016(x6) + + # Testcase 128 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest128 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest128: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend128: + + csrrw x0, mtvec, x31 + sd x25, 1024(x6) +sd x15, 1032(x6) + + # Testcase 130 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest130 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest130: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend130: + + csrrw x0, mtvec, x31 + sd x25, 1040(x6) +sd x15, 1048(x6) + + # Testcase 132 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest132 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest132: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 15 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend132: + + csrrw x0, mtvec, x31 + sd x25, 1056(x6) +sd x15, 1064(x6) + + # Testcase 134 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest134 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest134: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrci x0, marchid, 15 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend134: + + csrrw x0, mtvec, x31 + sd x25, 1072(x6) +sd x15, 1080(x6) + + # Testcase 136 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest136 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest136: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend136: + + csrrw x0, mtvec, x31 + sd x25, 1088(x6) +sd x15, 1096(x6) + + # Testcase 138 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest138 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest138: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 31 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend138: + + csrrw x0, mtvec, x31 + sd x25, 1104(x6) +sd x15, 1112(x6) + + # Testcase 140 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest140 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest140: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend140: + + csrrw x0, mtvec, x31 + sd x25, 1120(x6) +sd x15, 1128(x6) + + # Testcase 142 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest142 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest142: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend142: + + csrrw x0, mtvec, x31 + sd x25, 1136(x6) +sd x15, 1144(x6) + + # Testcase 144 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest144 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest144: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 16 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend144: + + csrrw x0, mtvec, x31 + sd x25, 1152(x6) +sd x15, 1160(x6) + + # Testcase 146 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest146 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest146: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrci x0, marchid, 16 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend146: + + csrrw x0, mtvec, x31 + sd x25, 1168(x6) +sd x15, 1176(x6) + + # Testcase 148 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest148 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest148: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend148: + + csrrw x0, mtvec, x31 + sd x25, 1184(x6) +sd x15, 1192(x6) + + # Testcase 150 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest150 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest150: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 21 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend150: + + csrrw x0, mtvec, x31 + sd x25, 1200(x6) +sd x15, 1208(x6) + + # Testcase 152 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest152 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest152: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend152: + + csrrw x0, mtvec, x31 + sd x25, 1216(x6) +sd x15, 1224(x6) + + # Testcase 154 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest154 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest154: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend154: + + csrrw x0, mtvec, x31 + sd x25, 1232(x6) +sd x15, 1240(x6) + + # Testcase 156 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest156 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest156: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 5 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend156: + + csrrw x0, mtvec, x31 + sd x25, 1248(x6) +sd x15, 1256(x6) + + # Testcase 158 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest158 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest158: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrci x0, marchid, 5 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend158: + + csrrw x0, mtvec, x31 + sd x25, 1264(x6) +sd x15, 1272(x6) + + # Testcase 160 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest160 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest160: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend160: + + csrrw x0, mtvec, x31 + sd x25, 1280(x6) +sd x15, 1288(x6) + + # Testcase 162 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest162 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest162: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 18 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend162: + + csrrw x0, mtvec, x31 + sd x25, 1296(x6) +sd x15, 1304(x6) + + # Testcase 164 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest164 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest164: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend164: + + csrrw x0, mtvec, x31 + sd x25, 1312(x6) +sd x15, 1320(x6) + + # Testcase 166 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest166 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest166: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend166: + + csrrw x0, mtvec, x31 + sd x25, 1328(x6) +sd x15, 1336(x6) + + # Testcase 168 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest168 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest168: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend168: + + csrrw x0, mtvec, x31 + sd x25, 1344(x6) +sd x15, 1352(x6) + + # Testcase 170 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest170 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest170: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrci x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend170: + + csrrw x0, mtvec, x31 + sd x25, 1360(x6) +sd x15, 1368(x6) + + # Testcase 172 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest172 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest172: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend172: + + csrrw x0, mtvec, x31 + sd x25, 1376(x6) +sd x15, 1384(x6) + + # Testcase 174 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest174 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest174: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 8 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend174: + + csrrw x0, mtvec, x31 + sd x25, 1392(x6) +sd x15, 1400(x6) + + # Testcase 176 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest176 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest176: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend176: + + csrrw x0, mtvec, x31 + sd x25, 1408(x6) +sd x15, 1416(x6) + + # Testcase 178 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest178 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest178: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend178: + + csrrw x0, mtvec, x31 + sd x25, 1424(x6) +sd x15, 1432(x6) + + # Testcase 180 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest180 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest180: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend180: + + csrrw x0, mtvec, x31 + sd x25, 1440(x6) +sd x15, 1448(x6) + + # Testcase 182 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest182 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest182: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrci x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend182: + + csrrw x0, mtvec, x31 + sd x25, 1456(x6) +sd x15, 1464(x6) + + # Testcase 184 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest184 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest184: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend184: + + csrrw x0, mtvec, x31 + sd x25, 1472(x6) +sd x15, 1480(x6) + + # Testcase 186 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest186 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest186: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 22 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend186: + + csrrw x0, mtvec, x31 + sd x25, 1488(x6) +sd x15, 1496(x6) + + # Testcase 188 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest188 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest188: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend188: + + csrrw x0, mtvec, x31 + sd x25, 1504(x6) +sd x15, 1512(x6) + + # Testcase 190 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest190 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest190: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend190: + + csrrw x0, mtvec, x31 + sd x25, 1520(x6) +sd x15, 1528(x6) + + # Testcase 192 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest192 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest192: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 6 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend192: + + csrrw x0, mtvec, x31 + sd x25, 1536(x6) +sd x15, 1544(x6) + + # Testcase 194 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest194 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest194: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrci x0, marchid, 6 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend194: + + csrrw x0, mtvec, x31 + sd x25, 1552(x6) +sd x15, 1560(x6) + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 196, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S new file mode 100644 index 00000000..ec00a2de --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S @@ -0,0 +1,2324 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MCAUSE.S +// dottolia@hmc.edu +// Created 2021-06-16 16:18:36.388509// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + + slli a0,a0,0x1f + slli a0,a0,0x1e + slli a0,a0,0x1d + slli a0,a0,0x1c + slli a0,a0,0x1b + slli a0,a0,0x1a + slli a0,a0,0x19 + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak + csrw mtvec, x1 + la x1, _j_s_trap_ebreak + csrw stvec, x1 + la x1, _j_u_trap_ebreak + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak + + # Machine mode traps + _j_m_trap_ebreak: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak + mret + + # Supervisor mode traps + _j_s_trap_ebreak: + li x25, 0xBAD00001 + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak: + j _j_goto_machine_mode_ebreak + + _j_goto_machine_mode_ebreak: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak: + + csrr x18, medeleg + li x9, 0 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0 + csrw mideleg, x9 + + la x28, _jtest0 + j _jdo0 + + _jtest0: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo0: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 0(x6) + + la x28, _jtest1 + j _jdo1 + + _jtest1: + + csrr x25, mcause + + + jr x27 + + _jdo1: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 8(x6) + + la x28, _jtest2 + j _jdo2 + + _jtest2: + + csrr x25, mcause + + + jr x27 + + _jdo2: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 16(x6) + + la x28, _jtest3 + j _jdo3 + + _jtest3: + + csrr x25, mcause + + + jr x27 + + _jdo3: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 24(x6) + + la x28, _jtest4 + j _jdo4 + + _jtest4: + + csrr x25, mcause + + + jr x27 + + _jdo4: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 32(x6) + + la x28, _jtest5 + j _jdo5 + + _jtest5: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo5: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 40(x6) + + la x28, _jtest6 + j _jdo6 + + _jtest6: + + csrr x25, mcause + + + jr x27 + + _jdo6: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 48(x6) + + la x28, _jtest7 + j _jdo7 + + _jtest7: + + csrr x25, mcause + + + jr x27 + + _jdo7: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 56(x6) + + la x28, _jtest8 + j _jdo8 + + _jtest8: + + csrr x25, mcause + + + jr x27 + + _jdo8: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 64(x6) + + la x28, _jtest9 + j _jdo9 + + _jtest9: + + csrr x25, mcause + + + jr x27 + + _jdo9: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 72(x6) + + la x28, _jtest10 + j _jdo10 + + _jtest10: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo10: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 80(x6) + + la x28, _jtest11 + j _jdo11 + + _jtest11: + + csrr x25, mcause + + + jr x27 + + _jdo11: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 88(x6) + + la x28, _jtest12 + j _jdo12 + + _jtest12: + + csrr x25, mcause + + + jr x27 + + _jdo12: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 96(x6) + + la x28, _jtest13 + j _jdo13 + + _jtest13: + + csrr x25, mcause + + + jr x27 + + _jdo13: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 104(x6) + + la x28, _jtest14 + j _jdo14 + + _jtest14: + + csrr x25, mcause + + + jr x27 + + _jdo14: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 112(x6) + + la x28, _jtest15 + j _jdo15 + + _jtest15: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo15: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 120(x6) + + la x28, _jtest16 + j _jdo16 + + _jtest16: + + csrr x25, mcause + + + jr x27 + + _jdo16: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 128(x6) + + la x28, _jtest17 + j _jdo17 + + _jtest17: + + csrr x25, mcause + + + jr x27 + + _jdo17: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 136(x6) + + la x28, _jtest18 + j _jdo18 + + _jtest18: + + csrr x25, mcause + + + jr x27 + + _jdo18: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 144(x6) + + la x28, _jtest19 + j _jdo19 + + _jtest19: + + csrr x25, mcause + + + jr x27 + + _jdo19: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 152(x6) + + la x28, _jtest20 + j _jdo20 + + _jtest20: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo20: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 160(x6) + + la x28, _jtest21 + j _jdo21 + + _jtest21: + + csrr x25, mcause + + + jr x27 + + _jdo21: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 168(x6) + + la x28, _jtest22 + j _jdo22 + + _jtest22: + + csrr x25, mcause + + + jr x27 + + _jdo22: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 176(x6) + + la x28, _jtest23 + j _jdo23 + + _jtest23: + + csrr x25, mcause + + + jr x27 + + _jdo23: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 184(x6) + + la x28, _jtest24 + j _jdo24 + + _jtest24: + + csrr x25, mcause + + + jr x27 + + _jdo24: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 192(x6) + + la x28, _jtest25 + j _jdo25 + + _jtest25: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo25: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 200(x6) + + la x28, _jtest26 + j _jdo26 + + _jtest26: + + csrr x25, mcause + + + jr x27 + + _jdo26: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 208(x6) + + la x28, _jtest27 + j _jdo27 + + _jtest27: + + csrr x25, mcause + + + jr x27 + + _jdo27: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 216(x6) + + la x28, _jtest28 + j _jdo28 + + _jtest28: + + csrr x25, mcause + + + jr x27 + + _jdo28: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 224(x6) + + la x28, _jtest29 + j _jdo29 + + _jtest29: + + csrr x25, mcause + + + jr x27 + + _jdo29: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 232(x6) + + la x28, _jtest30 + j _jdo30 + + _jtest30: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo30: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 240(x6) + + la x28, _jtest31 + j _jdo31 + + _jtest31: + + csrr x25, mcause + + + jr x27 + + _jdo31: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 248(x6) + + la x28, _jtest32 + j _jdo32 + + _jtest32: + + csrr x25, mcause + + + jr x27 + + _jdo32: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 256(x6) + + la x28, _jtest33 + j _jdo33 + + _jtest33: + + csrr x25, mcause + + + jr x27 + + _jdo33: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 264(x6) + + la x28, _jtest34 + j _jdo34 + + _jtest34: + + csrr x25, mcause + + + jr x27 + + _jdo34: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 272(x6) + + la x28, _jtest35 + j _jdo35 + + _jtest35: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo35: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 280(x6) + + la x28, _jtest36 + j _jdo36 + + _jtest36: + + csrr x25, mcause + + + jr x27 + + _jdo36: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 288(x6) + + la x28, _jtest37 + j _jdo37 + + _jtest37: + + csrr x25, mcause + + + jr x27 + + _jdo37: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 296(x6) + + la x28, _jtest38 + j _jdo38 + + _jtest38: + + csrr x25, mcause + + + jr x27 + + _jdo38: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 304(x6) + + la x28, _jtest39 + j _jdo39 + + _jtest39: + + csrr x25, mcause + + + jr x27 + + _jdo39: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 312(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + la x28, _jtest40 + j _jdo40 + + _jtest40: + + csrr x25, mcause + + + jr x27 + + _jdo40: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 320(x6) + + la x28, _jtest41 + j _jdo41 + + _jtest41: + + csrr x25, mcause + + + jr x27 + + _jdo41: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 328(x6) + + la x28, _jtest42 + j _jdo42 + + _jtest42: + + csrr x25, mcause + + + jr x27 + + _jdo42: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 336(x6) + + la x28, _jtest43 + j _jdo43 + + _jtest43: + + csrr x25, mcause + + + jr x27 + + _jdo43: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 344(x6) + + la x28, _jtest44 + j _jdo44 + + _jtest44: + + csrr x25, mcause + + + jr x27 + + _jdo44: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 352(x6) + + la x28, _jtest45 + j _jdo45 + + _jtest45: + + csrr x25, mcause + + + jr x27 + + _jdo45: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 360(x6) + + la x28, _jtest46 + j _jdo46 + + _jtest46: + + csrr x25, mcause + + + jr x27 + + _jdo46: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 368(x6) + + la x28, _jtest47 + j _jdo47 + + _jtest47: + + csrr x25, mcause + + + jr x27 + + _jdo47: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 376(x6) + + la x28, _jtest48 + j _jdo48 + + _jtest48: + + csrr x25, mcause + + + jr x27 + + _jdo48: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 384(x6) + + la x28, _jtest49 + j _jdo49 + + _jtest49: + + csrr x25, mcause + + + jr x27 + + _jdo49: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 392(x6) + + la x28, _jtest50 + j _jdo50 + + _jtest50: + + csrr x25, mcause + + + jr x27 + + _jdo50: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 400(x6) + + la x28, _jtest51 + j _jdo51 + + _jtest51: + + csrr x25, mcause + + + jr x27 + + _jdo51: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 408(x6) + + la x28, _jtest52 + j _jdo52 + + _jtest52: + + csrr x25, mcause + + + jr x27 + + _jdo52: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 416(x6) + + la x28, _jtest53 + j _jdo53 + + _jtest53: + + csrr x25, mcause + + + jr x27 + + _jdo53: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 424(x6) + + la x28, _jtest54 + j _jdo54 + + _jtest54: + + csrr x25, mcause + + + jr x27 + + _jdo54: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 432(x6) + + la x28, _jtest55 + j _jdo55 + + _jtest55: + + csrr x25, mcause + + + jr x27 + + _jdo55: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 440(x6) + + la x28, _jtest56 + j _jdo56 + + _jtest56: + + csrr x25, mcause + + + jr x27 + + _jdo56: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 448(x6) + + la x28, _jtest57 + j _jdo57 + + _jtest57: + + csrr x25, mcause + + + jr x27 + + _jdo57: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 456(x6) + + la x28, _jtest58 + j _jdo58 + + _jtest58: + + csrr x25, mcause + + + jr x27 + + _jdo58: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 464(x6) + + la x28, _jtest59 + j _jdo59 + + _jtest59: + + csrr x25, mcause + + + jr x27 + + _jdo59: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 472(x6) + + la x28, _jtest60 + j _jdo60 + + _jtest60: + + csrr x25, mcause + + + jr x27 + + _jdo60: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 480(x6) + + la x28, _jtest61 + j _jdo61 + + _jtest61: + + csrr x25, mcause + + + jr x27 + + _jdo61: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 488(x6) + + la x28, _jtest62 + j _jdo62 + + _jtest62: + + csrr x25, mcause + + + jr x27 + + _jdo62: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 496(x6) + + la x28, _jtest63 + j _jdo63 + + _jtest63: + + csrr x25, mcause + + + jr x27 + + _jdo63: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 504(x6) + + la x28, _jtest64 + j _jdo64 + + _jtest64: + + csrr x25, mcause + + + jr x27 + + _jdo64: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 512(x6) + + la x28, _jtest65 + j _jdo65 + + _jtest65: + + csrr x25, mcause + + + jr x27 + + _jdo65: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 520(x6) + + la x28, _jtest66 + j _jdo66 + + _jtest66: + + csrr x25, mcause + + + jr x27 + + _jdo66: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 528(x6) + + la x28, _jtest67 + j _jdo67 + + _jtest67: + + csrr x25, mcause + + + jr x27 + + _jdo67: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 536(x6) + + la x28, _jtest68 + j _jdo68 + + _jtest68: + + csrr x25, mcause + + + jr x27 + + _jdo68: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 544(x6) + + la x28, _jtest69 + j _jdo69 + + _jtest69: + + csrr x25, mcause + + + jr x27 + + _jdo69: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 552(x6) + + la x28, _jtest70 + j _jdo70 + + _jtest70: + + csrr x25, mcause + + + jr x27 + + _jdo70: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 560(x6) + + la x28, _jtest71 + j _jdo71 + + _jtest71: + + csrr x25, mcause + + + jr x27 + + _jdo71: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 568(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + la x28, _jtest72 + j _jdo72 + + _jtest72: + + csrr x25, mcause + + + jr x27 + + _jdo72: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 576(x6) + + la x28, _jtest73 + j _jdo73 + + _jtest73: + + csrr x25, mcause + + + jr x27 + + _jdo73: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 584(x6) + + la x28, _jtest74 + j _jdo74 + + _jtest74: + + csrr x25, mcause + + + jr x27 + + _jdo74: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 592(x6) + + la x28, _jtest75 + j _jdo75 + + _jtest75: + + csrr x25, mcause + + + jr x27 + + _jdo75: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 600(x6) + + la x28, _jtest76 + j _jdo76 + + _jtest76: + + csrr x25, mcause + + + jr x27 + + _jdo76: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 608(x6) + + la x28, _jtest77 + j _jdo77 + + _jtest77: + + csrr x25, mcause + + + jr x27 + + _jdo77: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 616(x6) + + la x28, _jtest78 + j _jdo78 + + _jtest78: + + csrr x25, mcause + + + jr x27 + + _jdo78: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 624(x6) + + la x28, _jtest79 + j _jdo79 + + _jtest79: + + csrr x25, mcause + + + jr x27 + + _jdo79: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 632(x6) + + la x28, _jtest80 + j _jdo80 + + _jtest80: + + csrr x25, mcause + + + jr x27 + + _jdo80: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 640(x6) + + la x28, _jtest81 + j _jdo81 + + _jtest81: + + csrr x25, mcause + + + jr x27 + + _jdo81: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 648(x6) + + la x28, _jtest82 + j _jdo82 + + _jtest82: + + csrr x25, mcause + + + jr x27 + + _jdo82: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 656(x6) + + la x28, _jtest83 + j _jdo83 + + _jtest83: + + csrr x25, mcause + + + jr x27 + + _jdo83: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 664(x6) + + la x28, _jtest84 + j _jdo84 + + _jtest84: + + csrr x25, mcause + + + jr x27 + + _jdo84: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 672(x6) + + la x28, _jtest85 + j _jdo85 + + _jtest85: + + csrr x25, mcause + + + jr x27 + + _jdo85: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 680(x6) + + la x28, _jtest86 + j _jdo86 + + _jtest86: + + csrr x25, mcause + + + jr x27 + + _jdo86: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 688(x6) + + la x28, _jtest87 + j _jdo87 + + _jtest87: + + csrr x25, mcause + + + jr x27 + + _jdo87: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 696(x6) + + la x28, _jtest88 + j _jdo88 + + _jtest88: + + csrr x25, mcause + + + jr x27 + + _jdo88: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 704(x6) + + la x28, _jtest89 + j _jdo89 + + _jtest89: + + csrr x25, mcause + + + jr x27 + + _jdo89: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 712(x6) + + la x28, _jtest90 + j _jdo90 + + _jtest90: + + csrr x25, mcause + + + jr x27 + + _jdo90: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 720(x6) + + la x28, _jtest91 + j _jdo91 + + _jtest91: + + csrr x25, mcause + + + jr x27 + + _jdo91: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 728(x6) + + la x28, _jtest92 + j _jdo92 + + _jtest92: + + csrr x25, mcause + + + jr x27 + + _jdo92: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 736(x6) + + la x28, _jtest93 + j _jdo93 + + _jtest93: + + csrr x25, mcause + + + jr x27 + + _jdo93: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 744(x6) + + la x28, _jtest94 + j _jdo94 + + _jtest94: + + csrr x25, mcause + + + jr x27 + + _jdo94: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 752(x6) + + la x28, _jtest95 + j _jdo95 + + _jtest95: + + csrr x25, mcause + + + jr x27 + + _jdo95: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 760(x6) + + la x28, _jtest96 + j _jdo96 + + _jtest96: + + csrr x25, mcause + + + jr x27 + + _jdo96: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 768(x6) + + la x28, _jtest97 + j _jdo97 + + _jtest97: + + csrr x25, mcause + + + jr x27 + + _jdo97: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 776(x6) + + la x28, _jtest98 + j _jdo98 + + _jtest98: + + csrr x25, mcause + + + jr x27 + + _jdo98: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 784(x6) + + la x28, _jtest99 + j _jdo99 + + _jtest99: + + csrr x25, mcause + + + jr x27 + + _jdo99: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 792(x6) + + la x28, _jtest100 + j _jdo100 + + _jtest100: + + csrr x25, mcause + + + jr x27 + + _jdo100: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 800(x6) + + la x28, _jtest101 + j _jdo101 + + _jtest101: + + csrr x25, mcause + + + jr x27 + + _jdo101: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 808(x6) + + la x28, _jtest102 + j _jdo102 + + _jtest102: + + csrr x25, mcause + + + jr x27 + + _jdo102: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 816(x6) + + la x28, _jtest103 + j _jdo103 + + _jtest103: + + csrr x25, mcause + + + jr x27 + + _jdo103: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 824(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 104, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S new file mode 100644 index 00000000..fb220ab6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S @@ -0,0 +1,3675 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MEDELEG.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:30.717084// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + csrr x18, medeleg + csrr x17, medeleg + + _start_0: + + la x1, _j_m_trap_0 + csrw mtvec, x1 + la x1, _j_s_trap_0 + csrw stvec, x1 + + j _j_test_0 + + _j_m_trap_0: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_0 + mret + + _j_s_trap_0: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_0 + sret + + _j_goto_machine_mode_0: + li x30, 1 + ebreak + + _j_test_0: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + .fill 1, 4, 0 + + + sd x25, 0(x6) + + _j_finished_0: + li x30, 0 + + _start_1: + + la x1, _j_m_trap_1 + csrw mtvec, x1 + la x1, _j_s_trap_1 + csrw stvec, x1 + + j _j_test_1 + + _j_m_trap_1: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_1 + mret + + _j_s_trap_1: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_1 + sret + + _j_goto_machine_mode_1: + li x30, 1 + ebreak + + _j_test_1: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + .fill 1, 4, 0 + + + sd x25, 8(x6) + + _j_finished_1: + li x30, 0 + + _start_2: + + la x1, _j_m_trap_2 + csrw mtvec, x1 + la x1, _j_s_trap_2 + csrw stvec, x1 + + j _j_test_2 + + _j_m_trap_2: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_2 + mret + + _j_s_trap_2: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_2 + sret + + _j_goto_machine_mode_2: + li x30, 1 + ebreak + + _j_test_2: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + .fill 1, 4, 0 + + + sd x25, 16(x6) + + j _j_goto_machine_mode_2 + + _j_finished_2: + li x30, 0 + + _start_3: + + la x1, _j_m_trap_3 + csrw mtvec, x1 + la x1, _j_s_trap_3 + csrw stvec, x1 + + j _j_test_3 + + _j_m_trap_3: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_3 + mret + + _j_s_trap_3: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_3 + sret + + _j_goto_machine_mode_3: + li x30, 1 + ebreak + + _j_test_3: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + .fill 1, 4, 0 + + + sd x25, 24(x6) + + j _j_goto_machine_mode_3 + + _j_finished_3: + li x30, 0 + + _start_4: + + la x1, _j_m_trap_4 + csrw mtvec, x1 + la x1, _j_s_trap_4 + csrw stvec, x1 + + j _j_test_4 + + _j_m_trap_4: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_4 + mret + + _j_s_trap_4: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_4 + sret + + _j_goto_machine_mode_4: + li x30, 1 + ebreak + + _j_test_4: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + .fill 1, 4, 0 + + + sd x25, 32(x6) + + j _j_goto_machine_mode_4 + + _j_finished_4: + li x30, 0 + + _start_5: + + la x1, _j_m_trap_5 + csrw mtvec, x1 + la x1, _j_s_trap_5 + csrw stvec, x1 + + j _j_test_5 + + _j_m_trap_5: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_5 + mret + + _j_s_trap_5: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_5 + sret + + _j_goto_machine_mode_5: + li x30, 1 + ebreak + + _j_test_5: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + .fill 1, 4, 0 + + + sd x25, 40(x6) + + j _j_goto_machine_mode_5 + + _j_finished_5: + li x30, 0 + + _start_6: + + la x1, _j_m_trap_6 + csrw mtvec, x1 + la x1, _j_s_trap_6 + csrw stvec, x1 + + j _j_test_6 + + _j_m_trap_6: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_6 + mret + + _j_s_trap_6: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_6 + sret + + _j_goto_machine_mode_6: + li x30, 1 + ecall + + _j_test_6: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + ebreak + + sd x25, 48(x6) + + _j_finished_6: + li x30, 0 + + _start_7: + + la x1, _j_m_trap_7 + csrw mtvec, x1 + la x1, _j_s_trap_7 + csrw stvec, x1 + + j _j_test_7 + + _j_m_trap_7: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_7 + mret + + _j_s_trap_7: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_7 + sret + + _j_goto_machine_mode_7: + li x30, 1 + ecall + + _j_test_7: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + ebreak + + sd x25, 56(x6) + + _j_finished_7: + li x30, 0 + + _start_8: + + la x1, _j_m_trap_8 + csrw mtvec, x1 + la x1, _j_s_trap_8 + csrw stvec, x1 + + j _j_test_8 + + _j_m_trap_8: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_8 + mret + + _j_s_trap_8: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_8 + sret + + _j_goto_machine_mode_8: + li x30, 1 + ecall + + _j_test_8: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ebreak + + sd x25, 64(x6) + + j _j_goto_machine_mode_8 + + _j_finished_8: + li x30, 0 + + _start_9: + + la x1, _j_m_trap_9 + csrw mtvec, x1 + la x1, _j_s_trap_9 + csrw stvec, x1 + + j _j_test_9 + + _j_m_trap_9: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_9 + mret + + _j_s_trap_9: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_9 + sret + + _j_goto_machine_mode_9: + li x30, 1 + ecall + + _j_test_9: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ebreak + + sd x25, 72(x6) + + j _j_goto_machine_mode_9 + + _j_finished_9: + li x30, 0 + + _start_10: + + la x1, _j_m_trap_10 + csrw mtvec, x1 + la x1, _j_s_trap_10 + csrw stvec, x1 + + j _j_test_10 + + _j_m_trap_10: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_10 + mret + + _j_s_trap_10: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_10 + sret + + _j_goto_machine_mode_10: + li x30, 1 + ecall + + _j_test_10: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ebreak + + sd x25, 80(x6) + + j _j_goto_machine_mode_10 + + _j_finished_10: + li x30, 0 + + _start_11: + + la x1, _j_m_trap_11 + csrw mtvec, x1 + la x1, _j_s_trap_11 + csrw stvec, x1 + + j _j_test_11 + + _j_m_trap_11: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_11 + mret + + _j_s_trap_11: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_11 + sret + + _j_goto_machine_mode_11: + li x30, 1 + ecall + + _j_test_11: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ebreak + + sd x25, 88(x6) + + j _j_goto_machine_mode_11 + + _j_finished_11: + li x30, 0 + + _start_12: + + la x1, _j_m_trap_12 + csrw mtvec, x1 + la x1, _j_s_trap_12 + csrw stvec, x1 + + j _j_test_12 + + _j_m_trap_12: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_12 + mret + + _j_s_trap_12: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_12 + sret + + _j_goto_machine_mode_12: + li x30, 1 + ebreak + + _j_test_12: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + lw x0, 11(x0) + + + sd x25, 96(x6) + + _j_finished_12: + li x30, 0 + + _start_13: + + la x1, _j_m_trap_13 + csrw mtvec, x1 + la x1, _j_s_trap_13 + csrw stvec, x1 + + j _j_test_13 + + _j_m_trap_13: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_13 + mret + + _j_s_trap_13: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_13 + sret + + _j_goto_machine_mode_13: + li x30, 1 + ebreak + + _j_test_13: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + lw x0, 11(x0) + + + sd x25, 104(x6) + + _j_finished_13: + li x30, 0 + + _start_14: + + la x1, _j_m_trap_14 + csrw mtvec, x1 + la x1, _j_s_trap_14 + csrw stvec, x1 + + j _j_test_14 + + _j_m_trap_14: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_14 + mret + + _j_s_trap_14: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_14 + sret + + _j_goto_machine_mode_14: + li x30, 1 + ebreak + + _j_test_14: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + lw x0, 11(x0) + + + sd x25, 112(x6) + + j _j_goto_machine_mode_14 + + _j_finished_14: + li x30, 0 + + _start_15: + + la x1, _j_m_trap_15 + csrw mtvec, x1 + la x1, _j_s_trap_15 + csrw stvec, x1 + + j _j_test_15 + + _j_m_trap_15: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_15 + mret + + _j_s_trap_15: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_15 + sret + + _j_goto_machine_mode_15: + li x30, 1 + ebreak + + _j_test_15: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + lw x0, 11(x0) + + + sd x25, 120(x6) + + j _j_goto_machine_mode_15 + + _j_finished_15: + li x30, 0 + + _start_16: + + la x1, _j_m_trap_16 + csrw mtvec, x1 + la x1, _j_s_trap_16 + csrw stvec, x1 + + j _j_test_16 + + _j_m_trap_16: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_16 + mret + + _j_s_trap_16: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_16 + sret + + _j_goto_machine_mode_16: + li x30, 1 + ebreak + + _j_test_16: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + lw x0, 11(x0) + + + sd x25, 128(x6) + + j _j_goto_machine_mode_16 + + _j_finished_16: + li x30, 0 + + _start_17: + + la x1, _j_m_trap_17 + csrw mtvec, x1 + la x1, _j_s_trap_17 + csrw stvec, x1 + + j _j_test_17 + + _j_m_trap_17: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_17 + mret + + _j_s_trap_17: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_17 + sret + + _j_goto_machine_mode_17: + li x30, 1 + ebreak + + _j_test_17: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + lw x0, 11(x0) + + + sd x25, 136(x6) + + j _j_goto_machine_mode_17 + + _j_finished_17: + li x30, 0 + + _start_18: + + la x1, _j_m_trap_18 + csrw mtvec, x1 + la x1, _j_s_trap_18 + csrw stvec, x1 + + j _j_test_18 + + _j_m_trap_18: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_18 + mret + + _j_s_trap_18: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_18 + sret + + _j_goto_machine_mode_18: + li x30, 1 + ebreak + + _j_test_18: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + sw x0, 11(x0) + + + sd x25, 144(x6) + + _j_finished_18: + li x30, 0 + + _start_19: + + la x1, _j_m_trap_19 + csrw mtvec, x1 + la x1, _j_s_trap_19 + csrw stvec, x1 + + j _j_test_19 + + _j_m_trap_19: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_19 + mret + + _j_s_trap_19: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_19 + sret + + _j_goto_machine_mode_19: + li x30, 1 + ebreak + + _j_test_19: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + sw x0, 11(x0) + + + sd x25, 152(x6) + + _j_finished_19: + li x30, 0 + + _start_20: + + la x1, _j_m_trap_20 + csrw mtvec, x1 + la x1, _j_s_trap_20 + csrw stvec, x1 + + j _j_test_20 + + _j_m_trap_20: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_20 + mret + + _j_s_trap_20: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_20 + sret + + _j_goto_machine_mode_20: + li x30, 1 + ebreak + + _j_test_20: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + sw x0, 11(x0) + + + sd x25, 160(x6) + + j _j_goto_machine_mode_20 + + _j_finished_20: + li x30, 0 + + _start_21: + + la x1, _j_m_trap_21 + csrw mtvec, x1 + la x1, _j_s_trap_21 + csrw stvec, x1 + + j _j_test_21 + + _j_m_trap_21: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_21 + mret + + _j_s_trap_21: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_21 + sret + + _j_goto_machine_mode_21: + li x30, 1 + ebreak + + _j_test_21: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + sw x0, 11(x0) + + + sd x25, 168(x6) + + j _j_goto_machine_mode_21 + + _j_finished_21: + li x30, 0 + + _start_22: + + la x1, _j_m_trap_22 + csrw mtvec, x1 + la x1, _j_s_trap_22 + csrw stvec, x1 + + j _j_test_22 + + _j_m_trap_22: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_22 + mret + + _j_s_trap_22: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_22 + sret + + _j_goto_machine_mode_22: + li x30, 1 + ebreak + + _j_test_22: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + sw x0, 11(x0) + + + sd x25, 176(x6) + + j _j_goto_machine_mode_22 + + _j_finished_22: + li x30, 0 + + _start_23: + + la x1, _j_m_trap_23 + csrw mtvec, x1 + la x1, _j_s_trap_23 + csrw stvec, x1 + + j _j_test_23 + + _j_m_trap_23: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_23 + mret + + _j_s_trap_23: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_23 + sret + + _j_goto_machine_mode_23: + li x30, 1 + ebreak + + _j_test_23: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + sw x0, 11(x0) + + + sd x25, 184(x6) + + j _j_goto_machine_mode_23 + + _j_finished_23: + li x30, 0 + + _start_24: + + la x1, _j_m_trap_24 + csrw mtvec, x1 + la x1, _j_s_trap_24 + csrw stvec, x1 + + j _j_test_24 + + _j_m_trap_24: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_24 + mret + + _j_s_trap_24: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_24 + sret + + _j_goto_machine_mode_24: + li x30, 1 + ebreak + + _j_test_24: + + li x25, 0xDEADBEA7 + + + li x1, 2048 + csrw medeleg, x1 + + + ecall + + sd x25, 192(x6) + + _j_finished_24: + li x30, 0 + + _start_25: + + la x1, _j_m_trap_25 + csrw mtvec, x1 + la x1, _j_s_trap_25 + csrw stvec, x1 + + j _j_test_25 + + _j_m_trap_25: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_25 + mret + + _j_s_trap_25: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_25 + sret + + _j_goto_machine_mode_25: + li x30, 1 + ebreak + + _j_test_25: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + ecall + + sd x25, 200(x6) + + _j_finished_25: + li x30, 0 + + _start_26: + + la x1, _j_m_trap_26 + csrw mtvec, x1 + la x1, _j_s_trap_26 + csrw stvec, x1 + + j _j_test_26 + + _j_m_trap_26: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_26 + mret + + _j_s_trap_26: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_26 + sret + + _j_goto_machine_mode_26: + li x30, 1 + ebreak + + _j_test_26: + + li x25, 0xDEADBEA7 + + + li x1, 512 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ecall + + sd x25, 208(x6) + + j _j_goto_machine_mode_26 + + _j_finished_26: + li x30, 0 + + _start_27: + + la x1, _j_m_trap_27 + csrw mtvec, x1 + la x1, _j_s_trap_27 + csrw stvec, x1 + + j _j_test_27 + + _j_m_trap_27: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_27 + mret + + _j_s_trap_27: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_27 + sret + + _j_goto_machine_mode_27: + li x30, 1 + ebreak + + _j_test_27: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ecall + + sd x25, 216(x6) + + j _j_goto_machine_mode_27 + + _j_finished_27: + li x30, 0 + + _start_28: + + la x1, _j_m_trap_28 + csrw mtvec, x1 + la x1, _j_s_trap_28 + csrw stvec, x1 + + j _j_test_28 + + _j_m_trap_28: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_28 + mret + + _j_s_trap_28: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_28 + sret + + _j_goto_machine_mode_28: + li x30, 1 + ebreak + + _j_test_28: + + li x25, 0xDEADBEA7 + + + li x1, 256 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ecall + + sd x25, 224(x6) + + j _j_goto_machine_mode_28 + + _j_finished_28: + li x30, 0 + + _start_29: + + la x1, _j_m_trap_29 + csrw mtvec, x1 + la x1, _j_s_trap_29 + csrw stvec, x1 + + j _j_test_29 + + _j_m_trap_29: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_29 + mret + + _j_s_trap_29: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_29 + sret + + _j_goto_machine_mode_29: + li x30, 1 + ebreak + + _j_test_29: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ecall + + sd x25, 232(x6) + + j _j_goto_machine_mode_29 + + _j_finished_29: + li x30, 0 + + _start_30: + + la x1, _j_m_trap_30 + csrw mtvec, x1 + la x1, _j_s_trap_30 + csrw stvec, x1 + + j _j_test_30 + + _j_m_trap_30: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_30 + mret + + _j_s_trap_30: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_30 + sret + + _j_goto_machine_mode_30: + li x30, 1 + ebreak + + _j_test_30: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + .fill 1, 4, 0 + + + sd x25, 240(x6) + + _j_finished_30: + li x30, 0 + + _start_31: + + la x1, _j_m_trap_31 + csrw mtvec, x1 + la x1, _j_s_trap_31 + csrw stvec, x1 + + j _j_test_31 + + _j_m_trap_31: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_31 + mret + + _j_s_trap_31: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_31 + sret + + _j_goto_machine_mode_31: + li x30, 1 + ebreak + + _j_test_31: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + .fill 1, 4, 0 + + + sd x25, 248(x6) + + _j_finished_31: + li x30, 0 + + _start_32: + + la x1, _j_m_trap_32 + csrw mtvec, x1 + la x1, _j_s_trap_32 + csrw stvec, x1 + + j _j_test_32 + + _j_m_trap_32: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_32 + mret + + _j_s_trap_32: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_32 + sret + + _j_goto_machine_mode_32: + li x30, 1 + ebreak + + _j_test_32: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + .fill 1, 4, 0 + + + sd x25, 256(x6) + + j _j_goto_machine_mode_32 + + _j_finished_32: + li x30, 0 + + _start_33: + + la x1, _j_m_trap_33 + csrw mtvec, x1 + la x1, _j_s_trap_33 + csrw stvec, x1 + + j _j_test_33 + + _j_m_trap_33: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_33 + mret + + _j_s_trap_33: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_33 + sret + + _j_goto_machine_mode_33: + li x30, 1 + ebreak + + _j_test_33: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + .fill 1, 4, 0 + + + sd x25, 264(x6) + + j _j_goto_machine_mode_33 + + _j_finished_33: + li x30, 0 + + _start_34: + + la x1, _j_m_trap_34 + csrw mtvec, x1 + la x1, _j_s_trap_34 + csrw stvec, x1 + + j _j_test_34 + + _j_m_trap_34: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_34 + mret + + _j_s_trap_34: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_34 + sret + + _j_goto_machine_mode_34: + li x30, 1 + ebreak + + _j_test_34: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + .fill 1, 4, 0 + + + sd x25, 272(x6) + + j _j_goto_machine_mode_34 + + _j_finished_34: + li x30, 0 + + _start_35: + + la x1, _j_m_trap_35 + csrw mtvec, x1 + la x1, _j_s_trap_35 + csrw stvec, x1 + + j _j_test_35 + + _j_m_trap_35: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_35 + mret + + _j_s_trap_35: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_35 + sret + + _j_goto_machine_mode_35: + li x30, 1 + ebreak + + _j_test_35: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + .fill 1, 4, 0 + + + sd x25, 280(x6) + + j _j_goto_machine_mode_35 + + _j_finished_35: + li x30, 0 + + _start_36: + + la x1, _j_m_trap_36 + csrw mtvec, x1 + la x1, _j_s_trap_36 + csrw stvec, x1 + + j _j_test_36 + + _j_m_trap_36: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_36 + mret + + _j_s_trap_36: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_36 + sret + + _j_goto_machine_mode_36: + li x30, 1 + ecall + + _j_test_36: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + ebreak + + sd x25, 288(x6) + + _j_finished_36: + li x30, 0 + + _start_37: + + la x1, _j_m_trap_37 + csrw mtvec, x1 + la x1, _j_s_trap_37 + csrw stvec, x1 + + j _j_test_37 + + _j_m_trap_37: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_37 + mret + + _j_s_trap_37: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_37 + sret + + _j_goto_machine_mode_37: + li x30, 1 + ecall + + _j_test_37: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + ebreak + + sd x25, 296(x6) + + _j_finished_37: + li x30, 0 + + _start_38: + + la x1, _j_m_trap_38 + csrw mtvec, x1 + la x1, _j_s_trap_38 + csrw stvec, x1 + + j _j_test_38 + + _j_m_trap_38: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_38 + mret + + _j_s_trap_38: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_38 + sret + + _j_goto_machine_mode_38: + li x30, 1 + ecall + + _j_test_38: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ebreak + + sd x25, 304(x6) + + j _j_goto_machine_mode_38 + + _j_finished_38: + li x30, 0 + + _start_39: + + la x1, _j_m_trap_39 + csrw mtvec, x1 + la x1, _j_s_trap_39 + csrw stvec, x1 + + j _j_test_39 + + _j_m_trap_39: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_39 + mret + + _j_s_trap_39: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_39 + sret + + _j_goto_machine_mode_39: + li x30, 1 + ecall + + _j_test_39: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ebreak + + sd x25, 312(x6) + + j _j_goto_machine_mode_39 + + _j_finished_39: + li x30, 0 + + _start_40: + + la x1, _j_m_trap_40 + csrw mtvec, x1 + la x1, _j_s_trap_40 + csrw stvec, x1 + + j _j_test_40 + + _j_m_trap_40: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_40 + mret + + _j_s_trap_40: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_40 + sret + + _j_goto_machine_mode_40: + li x30, 1 + ecall + + _j_test_40: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ebreak + + sd x25, 320(x6) + + j _j_goto_machine_mode_40 + + _j_finished_40: + li x30, 0 + + _start_41: + + la x1, _j_m_trap_41 + csrw mtvec, x1 + la x1, _j_s_trap_41 + csrw stvec, x1 + + j _j_test_41 + + _j_m_trap_41: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_41 + mret + + _j_s_trap_41: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_41 + sret + + _j_goto_machine_mode_41: + li x30, 1 + ecall + + _j_test_41: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ebreak + + sd x25, 328(x6) + + j _j_goto_machine_mode_41 + + _j_finished_41: + li x30, 0 + + _start_42: + + la x1, _j_m_trap_42 + csrw mtvec, x1 + la x1, _j_s_trap_42 + csrw stvec, x1 + + j _j_test_42 + + _j_m_trap_42: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_42 + mret + + _j_s_trap_42: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_42 + sret + + _j_goto_machine_mode_42: + li x30, 1 + ebreak + + _j_test_42: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + lw x0, 11(x0) + + + sd x25, 336(x6) + + _j_finished_42: + li x30, 0 + + _start_43: + + la x1, _j_m_trap_43 + csrw mtvec, x1 + la x1, _j_s_trap_43 + csrw stvec, x1 + + j _j_test_43 + + _j_m_trap_43: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_43 + mret + + _j_s_trap_43: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_43 + sret + + _j_goto_machine_mode_43: + li x30, 1 + ebreak + + _j_test_43: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + lw x0, 11(x0) + + + sd x25, 344(x6) + + _j_finished_43: + li x30, 0 + + _start_44: + + la x1, _j_m_trap_44 + csrw mtvec, x1 + la x1, _j_s_trap_44 + csrw stvec, x1 + + j _j_test_44 + + _j_m_trap_44: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_44 + mret + + _j_s_trap_44: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_44 + sret + + _j_goto_machine_mode_44: + li x30, 1 + ebreak + + _j_test_44: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + lw x0, 11(x0) + + + sd x25, 352(x6) + + j _j_goto_machine_mode_44 + + _j_finished_44: + li x30, 0 + + _start_45: + + la x1, _j_m_trap_45 + csrw mtvec, x1 + la x1, _j_s_trap_45 + csrw stvec, x1 + + j _j_test_45 + + _j_m_trap_45: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_45 + mret + + _j_s_trap_45: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_45 + sret + + _j_goto_machine_mode_45: + li x30, 1 + ebreak + + _j_test_45: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + lw x0, 11(x0) + + + sd x25, 360(x6) + + j _j_goto_machine_mode_45 + + _j_finished_45: + li x30, 0 + + _start_46: + + la x1, _j_m_trap_46 + csrw mtvec, x1 + la x1, _j_s_trap_46 + csrw stvec, x1 + + j _j_test_46 + + _j_m_trap_46: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_46 + mret + + _j_s_trap_46: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_46 + sret + + _j_goto_machine_mode_46: + li x30, 1 + ebreak + + _j_test_46: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + lw x0, 11(x0) + + + sd x25, 368(x6) + + j _j_goto_machine_mode_46 + + _j_finished_46: + li x30, 0 + + _start_47: + + la x1, _j_m_trap_47 + csrw mtvec, x1 + la x1, _j_s_trap_47 + csrw stvec, x1 + + j _j_test_47 + + _j_m_trap_47: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_47 + mret + + _j_s_trap_47: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_47 + sret + + _j_goto_machine_mode_47: + li x30, 1 + ebreak + + _j_test_47: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + lw x0, 11(x0) + + + sd x25, 376(x6) + + j _j_goto_machine_mode_47 + + _j_finished_47: + li x30, 0 + + _start_48: + + la x1, _j_m_trap_48 + csrw mtvec, x1 + la x1, _j_s_trap_48 + csrw stvec, x1 + + j _j_test_48 + + _j_m_trap_48: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_48 + mret + + _j_s_trap_48: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_48 + sret + + _j_goto_machine_mode_48: + li x30, 1 + ebreak + + _j_test_48: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + sw x0, 11(x0) + + + sd x25, 384(x6) + + _j_finished_48: + li x30, 0 + + _start_49: + + la x1, _j_m_trap_49 + csrw mtvec, x1 + la x1, _j_s_trap_49 + csrw stvec, x1 + + j _j_test_49 + + _j_m_trap_49: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_49 + mret + + _j_s_trap_49: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_49 + sret + + _j_goto_machine_mode_49: + li x30, 1 + ebreak + + _j_test_49: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + sw x0, 11(x0) + + + sd x25, 392(x6) + + _j_finished_49: + li x30, 0 + + _start_50: + + la x1, _j_m_trap_50 + csrw mtvec, x1 + la x1, _j_s_trap_50 + csrw stvec, x1 + + j _j_test_50 + + _j_m_trap_50: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_50 + mret + + _j_s_trap_50: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_50 + sret + + _j_goto_machine_mode_50: + li x30, 1 + ebreak + + _j_test_50: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + sw x0, 11(x0) + + + sd x25, 400(x6) + + j _j_goto_machine_mode_50 + + _j_finished_50: + li x30, 0 + + _start_51: + + la x1, _j_m_trap_51 + csrw mtvec, x1 + la x1, _j_s_trap_51 + csrw stvec, x1 + + j _j_test_51 + + _j_m_trap_51: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_51 + mret + + _j_s_trap_51: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_51 + sret + + _j_goto_machine_mode_51: + li x30, 1 + ebreak + + _j_test_51: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + sw x0, 11(x0) + + + sd x25, 408(x6) + + j _j_goto_machine_mode_51 + + _j_finished_51: + li x30, 0 + + _start_52: + + la x1, _j_m_trap_52 + csrw mtvec, x1 + la x1, _j_s_trap_52 + csrw stvec, x1 + + j _j_test_52 + + _j_m_trap_52: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_52 + mret + + _j_s_trap_52: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_52 + sret + + _j_goto_machine_mode_52: + li x30, 1 + ebreak + + _j_test_52: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + sw x0, 11(x0) + + + sd x25, 416(x6) + + j _j_goto_machine_mode_52 + + _j_finished_52: + li x30, 0 + + _start_53: + + la x1, _j_m_trap_53 + csrw mtvec, x1 + la x1, _j_s_trap_53 + csrw stvec, x1 + + j _j_test_53 + + _j_m_trap_53: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_53 + mret + + _j_s_trap_53: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_53 + sret + + _j_goto_machine_mode_53: + li x30, 1 + ebreak + + _j_test_53: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + sw x0, 11(x0) + + + sd x25, 424(x6) + + j _j_goto_machine_mode_53 + + _j_finished_53: + li x30, 0 + + _start_54: + + la x1, _j_m_trap_54 + csrw mtvec, x1 + la x1, _j_s_trap_54 + csrw stvec, x1 + + j _j_test_54 + + _j_m_trap_54: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_54 + mret + + _j_s_trap_54: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_54 + sret + + _j_goto_machine_mode_54: + li x30, 1 + ebreak + + _j_test_54: + + li x25, 0xDEADBEA7 + + + li x1, 2048 + csrw medeleg, x1 + + + ecall + + sd x25, 432(x6) + + _j_finished_54: + li x30, 0 + + _start_55: + + la x1, _j_m_trap_55 + csrw mtvec, x1 + la x1, _j_s_trap_55 + csrw stvec, x1 + + j _j_test_55 + + _j_m_trap_55: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_55 + mret + + _j_s_trap_55: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_55 + sret + + _j_goto_machine_mode_55: + li x30, 1 + ebreak + + _j_test_55: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + ecall + + sd x25, 440(x6) + + _j_finished_55: + li x30, 0 + + _start_56: + + la x1, _j_m_trap_56 + csrw mtvec, x1 + la x1, _j_s_trap_56 + csrw stvec, x1 + + j _j_test_56 + + _j_m_trap_56: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_56 + mret + + _j_s_trap_56: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_56 + sret + + _j_goto_machine_mode_56: + li x30, 1 + ebreak + + _j_test_56: + + li x25, 0xDEADBEA7 + + + li x1, 512 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ecall + + sd x25, 448(x6) + + j _j_goto_machine_mode_56 + + _j_finished_56: + li x30, 0 + + _start_57: + + la x1, _j_m_trap_57 + csrw mtvec, x1 + la x1, _j_s_trap_57 + csrw stvec, x1 + + j _j_test_57 + + _j_m_trap_57: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_57 + mret + + _j_s_trap_57: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_57 + sret + + _j_goto_machine_mode_57: + li x30, 1 + ebreak + + _j_test_57: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ecall + + sd x25, 456(x6) + + j _j_goto_machine_mode_57 + + _j_finished_57: + li x30, 0 + + _start_58: + + la x1, _j_m_trap_58 + csrw mtvec, x1 + la x1, _j_s_trap_58 + csrw stvec, x1 + + j _j_test_58 + + _j_m_trap_58: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_58 + mret + + _j_s_trap_58: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_58 + sret + + _j_goto_machine_mode_58: + li x30, 1 + ebreak + + _j_test_58: + + li x25, 0xDEADBEA7 + + + li x1, 256 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ecall + + sd x25, 464(x6) + + j _j_goto_machine_mode_58 + + _j_finished_58: + li x30, 0 + + _start_59: + + la x1, _j_m_trap_59 + csrw mtvec, x1 + la x1, _j_s_trap_59 + csrw stvec, x1 + + j _j_test_59 + + _j_m_trap_59: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_59 + mret + + _j_s_trap_59: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_59 + sret + + _j_goto_machine_mode_59: + li x30, 1 + ebreak + + _j_test_59: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ecall + + sd x25, 472(x6) + + j _j_goto_machine_mode_59 + + _j_finished_59: + li x30, 0 + + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x17 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 60, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S new file mode 100644 index 00000000..0db38c54 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S @@ -0,0 +1,3778 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MHARTID.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:52.358935// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + # Testcase 0 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest0 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest0: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend0: + + csrrw x0, mtvec, x31 + sd x25, 0(x6) +sd x15, 8(x6) + + # Testcase 2 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest2 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest2: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 0 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend2: + + csrrw x0, mtvec, x31 + sd x25, 16(x6) +sd x15, 24(x6) + + # Testcase 4 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest4 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest4: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend4: + + csrrw x0, mtvec, x31 + sd x25, 32(x6) +sd x15, 40(x6) + + # Testcase 6 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest6 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest6: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 1 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend6: + + csrrw x0, mtvec, x31 + sd x25, 48(x6) +sd x15, 56(x6) + + # Testcase 8 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest8 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest8: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend8: + + csrrw x0, mtvec, x31 + sd x25, 64(x6) +sd x15, 72(x6) + + # Testcase 10 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest10 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest10: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend10: + + csrrw x0, mtvec, x31 + sd x25, 80(x6) +sd x15, 88(x6) + + # Testcase 12 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest12 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest12: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend12: + + csrrw x0, mtvec, x31 + sd x25, 96(x6) +sd x15, 104(x6) + + # Testcase 14 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest14 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest14: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend14: + + csrrw x0, mtvec, x31 + sd x25, 112(x6) +sd x15, 120(x6) + + # Testcase 16 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest16 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest16: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend16: + + csrrw x0, mtvec, x31 + sd x25, 128(x6) +sd x15, 136(x6) + + # Testcase 18 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest18 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest18: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend18: + + csrrw x0, mtvec, x31 + sd x25, 144(x6) +sd x15, 152(x6) + + # Testcase 20 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest20 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest20: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend20: + + csrrw x0, mtvec, x31 + sd x25, 160(x6) +sd x15, 168(x6) + + # Testcase 22 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest22 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest22: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend22: + + csrrw x0, mtvec, x31 + sd x25, 176(x6) +sd x15, 184(x6) + + # Testcase 24 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest24 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest24: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 3 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend24: + + csrrw x0, mtvec, x31 + sd x25, 192(x6) +sd x15, 200(x6) + + # Testcase 26 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest26 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest26: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 3 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend26: + + csrrw x0, mtvec, x31 + sd x25, 208(x6) +sd x15, 216(x6) + + # Testcase 28 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest28 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest28: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend28: + + csrrw x0, mtvec, x31 + sd x25, 224(x6) +sd x15, 232(x6) + + # Testcase 30 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest30 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest30: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 31 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend30: + + csrrw x0, mtvec, x31 + sd x25, 240(x6) +sd x15, 248(x6) + + # Testcase 32 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest32 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest32: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend32: + + csrrw x0, mtvec, x31 + sd x25, 256(x6) +sd x15, 264(x6) + + # Testcase 34 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest34 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest34: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend34: + + csrrw x0, mtvec, x31 + sd x25, 272(x6) +sd x15, 280(x6) + + # Testcase 36 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest36 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest36: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 1 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend36: + + csrrw x0, mtvec, x31 + sd x25, 288(x6) +sd x15, 296(x6) + + # Testcase 38 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest38 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest38: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 1 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend38: + + csrrw x0, mtvec, x31 + sd x25, 304(x6) +sd x15, 312(x6) + + # Testcase 40 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest40 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest40: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend40: + + csrrw x0, mtvec, x31 + sd x25, 320(x6) +sd x15, 328(x6) + + # Testcase 42 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest42 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest42: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 0 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend42: + + csrrw x0, mtvec, x31 + sd x25, 336(x6) +sd x15, 344(x6) + + # Testcase 44 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest44 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest44: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend44: + + csrrw x0, mtvec, x31 + sd x25, 352(x6) +sd x15, 360(x6) + + # Testcase 46 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest46 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest46: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend46: + + csrrw x0, mtvec, x31 + sd x25, 368(x6) +sd x15, 376(x6) + + # Testcase 48 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest48 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest48: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend48: + + csrrw x0, mtvec, x31 + sd x25, 384(x6) +sd x15, 392(x6) + + # Testcase 50 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest50 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest50: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend50: + + csrrw x0, mtvec, x31 + sd x25, 400(x6) +sd x15, 408(x6) + + # Testcase 52 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest52 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest52: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend52: + + csrrw x0, mtvec, x31 + sd x25, 416(x6) +sd x15, 424(x6) + + # Testcase 54 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest54 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest54: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 20 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend54: + + csrrw x0, mtvec, x31 + sd x25, 432(x6) +sd x15, 440(x6) + + # Testcase 56 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest56 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest56: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend56: + + csrrw x0, mtvec, x31 + sd x25, 448(x6) +sd x15, 456(x6) + + # Testcase 58 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest58 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest58: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend58: + + csrrw x0, mtvec, x31 + sd x25, 464(x6) +sd x15, 472(x6) + + # Testcase 60 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest60 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest60: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 28 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend60: + + csrrw x0, mtvec, x31 + sd x25, 480(x6) +sd x15, 488(x6) + + # Testcase 62 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest62 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest62: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 28 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend62: + + csrrw x0, mtvec, x31 + sd x25, 496(x6) +sd x15, 504(x6) + + # Testcase 64 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest64 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest64: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend64: + + csrrw x0, mtvec, x31 + sd x25, 512(x6) +sd x15, 520(x6) + + # Testcase 66 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest66 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest66: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 30 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend66: + + csrrw x0, mtvec, x31 + sd x25, 528(x6) +sd x15, 536(x6) + + # Testcase 68 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest68 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest68: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend68: + + csrrw x0, mtvec, x31 + sd x25, 544(x6) +sd x15, 552(x6) + + # Testcase 70 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest70 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest70: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend70: + + csrrw x0, mtvec, x31 + sd x25, 560(x6) +sd x15, 568(x6) + + # Testcase 72 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest72 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest72: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 7 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend72: + + csrrw x0, mtvec, x31 + sd x25, 576(x6) +sd x15, 584(x6) + + # Testcase 74 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest74 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest74: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 7 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend74: + + csrrw x0, mtvec, x31 + sd x25, 592(x6) +sd x15, 600(x6) + + # Testcase 76 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest76 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest76: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend76: + + csrrw x0, mtvec, x31 + sd x25, 608(x6) +sd x15, 616(x6) + + # Testcase 78 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest78 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest78: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 31 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend78: + + csrrw x0, mtvec, x31 + sd x25, 624(x6) +sd x15, 632(x6) + + # Testcase 80 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest80 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest80: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend80: + + csrrw x0, mtvec, x31 + sd x25, 640(x6) +sd x15, 648(x6) + + # Testcase 82 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest82 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest82: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend82: + + csrrw x0, mtvec, x31 + sd x25, 656(x6) +sd x15, 664(x6) + + # Testcase 84 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest84 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest84: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 8 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend84: + + csrrw x0, mtvec, x31 + sd x25, 672(x6) +sd x15, 680(x6) + + # Testcase 86 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest86 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest86: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 8 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend86: + + csrrw x0, mtvec, x31 + sd x25, 688(x6) +sd x15, 696(x6) + + # Testcase 88 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest88 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest88: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend88: + + csrrw x0, mtvec, x31 + sd x25, 704(x6) +sd x15, 712(x6) + + # Testcase 90 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest90 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest90: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 0 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend90: + + csrrw x0, mtvec, x31 + sd x25, 720(x6) +sd x15, 728(x6) + + # Testcase 92 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest92 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest92: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend92: + + csrrw x0, mtvec, x31 + sd x25, 736(x6) +sd x15, 744(x6) + + # Testcase 94 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest94 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest94: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend94: + + csrrw x0, mtvec, x31 + sd x25, 752(x6) +sd x15, 760(x6) + + # Testcase 96 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest96 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest96: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 9 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend96: + + csrrw x0, mtvec, x31 + sd x25, 768(x6) +sd x15, 776(x6) + + # Testcase 98 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest98 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest98: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 9 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend98: + + csrrw x0, mtvec, x31 + sd x25, 784(x6) +sd x15, 792(x6) + + # Testcase 100 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest100 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest100: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend100: + + csrrw x0, mtvec, x31 + sd x25, 800(x6) +sd x15, 808(x6) + + # Testcase 102 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest102 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest102: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 1 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend102: + + csrrw x0, mtvec, x31 + sd x25, 816(x6) +sd x15, 824(x6) + + # Testcase 104 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest104 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest104: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend104: + + csrrw x0, mtvec, x31 + sd x25, 832(x6) +sd x15, 840(x6) + + # Testcase 106 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest106 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest106: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend106: + + csrrw x0, mtvec, x31 + sd x25, 848(x6) +sd x15, 856(x6) + + # Testcase 108 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest108 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest108: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 10 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend108: + + csrrw x0, mtvec, x31 + sd x25, 864(x6) +sd x15, 872(x6) + + # Testcase 110 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest110 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest110: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 10 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend110: + + csrrw x0, mtvec, x31 + sd x25, 880(x6) +sd x15, 888(x6) + + # Testcase 112 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest112 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest112: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend112: + + csrrw x0, mtvec, x31 + sd x25, 896(x6) +sd x15, 904(x6) + + # Testcase 114 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest114 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest114: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend114: + + csrrw x0, mtvec, x31 + sd x25, 912(x6) +sd x15, 920(x6) + + # Testcase 116 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest116 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest116: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend116: + + csrrw x0, mtvec, x31 + sd x25, 928(x6) +sd x15, 936(x6) + + # Testcase 118 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest118 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest118: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend118: + + csrrw x0, mtvec, x31 + sd x25, 944(x6) +sd x15, 952(x6) + + # Testcase 120 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest120 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest120: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 20 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend120: + + csrrw x0, mtvec, x31 + sd x25, 960(x6) +sd x15, 968(x6) + + # Testcase 122 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest122 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest122: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 20 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend122: + + csrrw x0, mtvec, x31 + sd x25, 976(x6) +sd x15, 984(x6) + + # Testcase 124 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest124 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest124: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend124: + + csrrw x0, mtvec, x31 + sd x25, 992(x6) +sd x15, 1000(x6) + + # Testcase 126 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest126 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest126: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 30 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend126: + + csrrw x0, mtvec, x31 + sd x25, 1008(x6) +sd x15, 1016(x6) + + # Testcase 128 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest128 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest128: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend128: + + csrrw x0, mtvec, x31 + sd x25, 1024(x6) +sd x15, 1032(x6) + + # Testcase 130 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest130 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest130: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend130: + + csrrw x0, mtvec, x31 + sd x25, 1040(x6) +sd x15, 1048(x6) + + # Testcase 132 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest132 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest132: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 15 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend132: + + csrrw x0, mtvec, x31 + sd x25, 1056(x6) +sd x15, 1064(x6) + + # Testcase 134 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest134 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest134: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 15 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend134: + + csrrw x0, mtvec, x31 + sd x25, 1072(x6) +sd x15, 1080(x6) + + # Testcase 136 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest136 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest136: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend136: + + csrrw x0, mtvec, x31 + sd x25, 1088(x6) +sd x15, 1096(x6) + + # Testcase 138 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest138 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest138: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 31 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend138: + + csrrw x0, mtvec, x31 + sd x25, 1104(x6) +sd x15, 1112(x6) + + # Testcase 140 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest140 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest140: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend140: + + csrrw x0, mtvec, x31 + sd x25, 1120(x6) +sd x15, 1128(x6) + + # Testcase 142 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest142 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest142: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend142: + + csrrw x0, mtvec, x31 + sd x25, 1136(x6) +sd x15, 1144(x6) + + # Testcase 144 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest144 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest144: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 16 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend144: + + csrrw x0, mtvec, x31 + sd x25, 1152(x6) +sd x15, 1160(x6) + + # Testcase 146 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest146 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest146: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 16 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend146: + + csrrw x0, mtvec, x31 + sd x25, 1168(x6) +sd x15, 1176(x6) + + # Testcase 148 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest148 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest148: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend148: + + csrrw x0, mtvec, x31 + sd x25, 1184(x6) +sd x15, 1192(x6) + + # Testcase 150 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest150 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest150: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 19 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend150: + + csrrw x0, mtvec, x31 + sd x25, 1200(x6) +sd x15, 1208(x6) + + # Testcase 152 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest152 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest152: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend152: + + csrrw x0, mtvec, x31 + sd x25, 1216(x6) +sd x15, 1224(x6) + + # Testcase 154 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest154 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest154: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend154: + + csrrw x0, mtvec, x31 + sd x25, 1232(x6) +sd x15, 1240(x6) + + # Testcase 156 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest156 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest156: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 27 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend156: + + csrrw x0, mtvec, x31 + sd x25, 1248(x6) +sd x15, 1256(x6) + + # Testcase 158 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest158 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest158: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 27 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend158: + + csrrw x0, mtvec, x31 + sd x25, 1264(x6) +sd x15, 1272(x6) + + # Testcase 160 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest160 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest160: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend160: + + csrrw x0, mtvec, x31 + sd x25, 1280(x6) +sd x15, 1288(x6) + + # Testcase 162 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest162 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest162: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 26 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend162: + + csrrw x0, mtvec, x31 + sd x25, 1296(x6) +sd x15, 1304(x6) + + # Testcase 164 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest164 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest164: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend164: + + csrrw x0, mtvec, x31 + sd x25, 1312(x6) +sd x15, 1320(x6) + + # Testcase 166 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest166 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest166: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend166: + + csrrw x0, mtvec, x31 + sd x25, 1328(x6) +sd x15, 1336(x6) + + # Testcase 168 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest168 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest168: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend168: + + csrrw x0, mtvec, x31 + sd x25, 1344(x6) +sd x15, 1352(x6) + + # Testcase 170 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest170 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest170: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend170: + + csrrw x0, mtvec, x31 + sd x25, 1360(x6) +sd x15, 1368(x6) + + # Testcase 172 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest172 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest172: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend172: + + csrrw x0, mtvec, x31 + sd x25, 1376(x6) +sd x15, 1384(x6) + + # Testcase 174 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest174 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest174: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend174: + + csrrw x0, mtvec, x31 + sd x25, 1392(x6) +sd x15, 1400(x6) + + # Testcase 176 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest176 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest176: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend176: + + csrrw x0, mtvec, x31 + sd x25, 1408(x6) +sd x15, 1416(x6) + + # Testcase 178 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest178 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest178: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend178: + + csrrw x0, mtvec, x31 + sd x25, 1424(x6) +sd x15, 1432(x6) + + # Testcase 180 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest180 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest180: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend180: + + csrrw x0, mtvec, x31 + sd x25, 1440(x6) +sd x15, 1448(x6) + + # Testcase 182 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest182 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest182: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend182: + + csrrw x0, mtvec, x31 + sd x25, 1456(x6) +sd x15, 1464(x6) + + # Testcase 184 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest184 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest184: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend184: + + csrrw x0, mtvec, x31 + sd x25, 1472(x6) +sd x15, 1480(x6) + + # Testcase 186 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest186 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest186: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 25 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend186: + + csrrw x0, mtvec, x31 + sd x25, 1488(x6) +sd x15, 1496(x6) + + # Testcase 188 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest188 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest188: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend188: + + csrrw x0, mtvec, x31 + sd x25, 1504(x6) +sd x15, 1512(x6) + + # Testcase 190 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest190 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest190: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend190: + + csrrw x0, mtvec, x31 + sd x25, 1520(x6) +sd x15, 1528(x6) + + # Testcase 192 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest192 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest192: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 8 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend192: + + csrrw x0, mtvec, x31 + sd x25, 1536(x6) +sd x15, 1544(x6) + + # Testcase 194 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest194 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest194: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 8 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend194: + + csrrw x0, mtvec, x31 + sd x25, 1552(x6) +sd x15, 1560(x6) + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 196, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIMPID.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIMPID.S new file mode 100644 index 00000000..851c78db --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIMPID.S @@ -0,0 +1,3778 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MIMPID.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:52.364454// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + # Testcase 0 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest0 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest0: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend0: + + csrrw x0, mtvec, x31 + sd x25, 0(x6) +sd x15, 8(x6) + + # Testcase 2 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest2 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest2: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 0 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend2: + + csrrw x0, mtvec, x31 + sd x25, 16(x6) +sd x15, 24(x6) + + # Testcase 4 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest4 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest4: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend4: + + csrrw x0, mtvec, x31 + sd x25, 32(x6) +sd x15, 40(x6) + + # Testcase 6 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest6 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest6: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 1 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend6: + + csrrw x0, mtvec, x31 + sd x25, 48(x6) +sd x15, 56(x6) + + # Testcase 8 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest8 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest8: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend8: + + csrrw x0, mtvec, x31 + sd x25, 64(x6) +sd x15, 72(x6) + + # Testcase 10 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest10 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest10: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend10: + + csrrw x0, mtvec, x31 + sd x25, 80(x6) +sd x15, 88(x6) + + # Testcase 12 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest12 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest12: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend12: + + csrrw x0, mtvec, x31 + sd x25, 96(x6) +sd x15, 104(x6) + + # Testcase 14 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest14 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest14: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend14: + + csrrw x0, mtvec, x31 + sd x25, 112(x6) +sd x15, 120(x6) + + # Testcase 16 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest16 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest16: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend16: + + csrrw x0, mtvec, x31 + sd x25, 128(x6) +sd x15, 136(x6) + + # Testcase 18 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest18 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest18: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend18: + + csrrw x0, mtvec, x31 + sd x25, 144(x6) +sd x15, 152(x6) + + # Testcase 20 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest20 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest20: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend20: + + csrrw x0, mtvec, x31 + sd x25, 160(x6) +sd x15, 168(x6) + + # Testcase 22 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest22 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest22: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend22: + + csrrw x0, mtvec, x31 + sd x25, 176(x6) +sd x15, 184(x6) + + # Testcase 24 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest24 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest24: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 3 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend24: + + csrrw x0, mtvec, x31 + sd x25, 192(x6) +sd x15, 200(x6) + + # Testcase 26 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest26 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest26: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 3 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend26: + + csrrw x0, mtvec, x31 + sd x25, 208(x6) +sd x15, 216(x6) + + # Testcase 28 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest28 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest28: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend28: + + csrrw x0, mtvec, x31 + sd x25, 224(x6) +sd x15, 232(x6) + + # Testcase 30 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest30 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest30: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 31 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend30: + + csrrw x0, mtvec, x31 + sd x25, 240(x6) +sd x15, 248(x6) + + # Testcase 32 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest32 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest32: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend32: + + csrrw x0, mtvec, x31 + sd x25, 256(x6) +sd x15, 264(x6) + + # Testcase 34 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest34 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest34: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend34: + + csrrw x0, mtvec, x31 + sd x25, 272(x6) +sd x15, 280(x6) + + # Testcase 36 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest36 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest36: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 1 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend36: + + csrrw x0, mtvec, x31 + sd x25, 288(x6) +sd x15, 296(x6) + + # Testcase 38 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest38 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest38: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 1 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend38: + + csrrw x0, mtvec, x31 + sd x25, 304(x6) +sd x15, 312(x6) + + # Testcase 40 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest40 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest40: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend40: + + csrrw x0, mtvec, x31 + sd x25, 320(x6) +sd x15, 328(x6) + + # Testcase 42 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest42 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest42: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 0 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend42: + + csrrw x0, mtvec, x31 + sd x25, 336(x6) +sd x15, 344(x6) + + # Testcase 44 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest44 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest44: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend44: + + csrrw x0, mtvec, x31 + sd x25, 352(x6) +sd x15, 360(x6) + + # Testcase 46 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest46 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest46: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend46: + + csrrw x0, mtvec, x31 + sd x25, 368(x6) +sd x15, 376(x6) + + # Testcase 48 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest48 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest48: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend48: + + csrrw x0, mtvec, x31 + sd x25, 384(x6) +sd x15, 392(x6) + + # Testcase 50 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest50 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest50: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend50: + + csrrw x0, mtvec, x31 + sd x25, 400(x6) +sd x15, 408(x6) + + # Testcase 52 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest52 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest52: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend52: + + csrrw x0, mtvec, x31 + sd x25, 416(x6) +sd x15, 424(x6) + + # Testcase 54 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest54 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest54: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 20 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend54: + + csrrw x0, mtvec, x31 + sd x25, 432(x6) +sd x15, 440(x6) + + # Testcase 56 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest56 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest56: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend56: + + csrrw x0, mtvec, x31 + sd x25, 448(x6) +sd x15, 456(x6) + + # Testcase 58 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest58 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest58: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend58: + + csrrw x0, mtvec, x31 + sd x25, 464(x6) +sd x15, 472(x6) + + # Testcase 60 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest60 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest60: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 28 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend60: + + csrrw x0, mtvec, x31 + sd x25, 480(x6) +sd x15, 488(x6) + + # Testcase 62 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest62 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest62: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 28 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend62: + + csrrw x0, mtvec, x31 + sd x25, 496(x6) +sd x15, 504(x6) + + # Testcase 64 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest64 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest64: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend64: + + csrrw x0, mtvec, x31 + sd x25, 512(x6) +sd x15, 520(x6) + + # Testcase 66 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest66 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest66: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 30 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend66: + + csrrw x0, mtvec, x31 + sd x25, 528(x6) +sd x15, 536(x6) + + # Testcase 68 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest68 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest68: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend68: + + csrrw x0, mtvec, x31 + sd x25, 544(x6) +sd x15, 552(x6) + + # Testcase 70 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest70 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest70: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend70: + + csrrw x0, mtvec, x31 + sd x25, 560(x6) +sd x15, 568(x6) + + # Testcase 72 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest72 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest72: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 7 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend72: + + csrrw x0, mtvec, x31 + sd x25, 576(x6) +sd x15, 584(x6) + + # Testcase 74 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest74 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest74: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 7 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend74: + + csrrw x0, mtvec, x31 + sd x25, 592(x6) +sd x15, 600(x6) + + # Testcase 76 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest76 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest76: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend76: + + csrrw x0, mtvec, x31 + sd x25, 608(x6) +sd x15, 616(x6) + + # Testcase 78 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest78 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest78: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 31 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend78: + + csrrw x0, mtvec, x31 + sd x25, 624(x6) +sd x15, 632(x6) + + # Testcase 80 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest80 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest80: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend80: + + csrrw x0, mtvec, x31 + sd x25, 640(x6) +sd x15, 648(x6) + + # Testcase 82 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest82 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest82: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend82: + + csrrw x0, mtvec, x31 + sd x25, 656(x6) +sd x15, 664(x6) + + # Testcase 84 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest84 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest84: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 8 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend84: + + csrrw x0, mtvec, x31 + sd x25, 672(x6) +sd x15, 680(x6) + + # Testcase 86 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest86 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest86: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 8 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend86: + + csrrw x0, mtvec, x31 + sd x25, 688(x6) +sd x15, 696(x6) + + # Testcase 88 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest88 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest88: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend88: + + csrrw x0, mtvec, x31 + sd x25, 704(x6) +sd x15, 712(x6) + + # Testcase 90 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest90 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest90: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 0 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend90: + + csrrw x0, mtvec, x31 + sd x25, 720(x6) +sd x15, 728(x6) + + # Testcase 92 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest92 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest92: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend92: + + csrrw x0, mtvec, x31 + sd x25, 736(x6) +sd x15, 744(x6) + + # Testcase 94 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest94 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest94: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend94: + + csrrw x0, mtvec, x31 + sd x25, 752(x6) +sd x15, 760(x6) + + # Testcase 96 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest96 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest96: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 9 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend96: + + csrrw x0, mtvec, x31 + sd x25, 768(x6) +sd x15, 776(x6) + + # Testcase 98 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest98 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest98: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 9 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend98: + + csrrw x0, mtvec, x31 + sd x25, 784(x6) +sd x15, 792(x6) + + # Testcase 100 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest100 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest100: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend100: + + csrrw x0, mtvec, x31 + sd x25, 800(x6) +sd x15, 808(x6) + + # Testcase 102 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest102 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest102: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 1 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend102: + + csrrw x0, mtvec, x31 + sd x25, 816(x6) +sd x15, 824(x6) + + # Testcase 104 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest104 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest104: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend104: + + csrrw x0, mtvec, x31 + sd x25, 832(x6) +sd x15, 840(x6) + + # Testcase 106 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest106 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest106: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend106: + + csrrw x0, mtvec, x31 + sd x25, 848(x6) +sd x15, 856(x6) + + # Testcase 108 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest108 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest108: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 10 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend108: + + csrrw x0, mtvec, x31 + sd x25, 864(x6) +sd x15, 872(x6) + + # Testcase 110 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest110 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest110: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 10 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend110: + + csrrw x0, mtvec, x31 + sd x25, 880(x6) +sd x15, 888(x6) + + # Testcase 112 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest112 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest112: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend112: + + csrrw x0, mtvec, x31 + sd x25, 896(x6) +sd x15, 904(x6) + + # Testcase 114 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest114 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest114: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend114: + + csrrw x0, mtvec, x31 + sd x25, 912(x6) +sd x15, 920(x6) + + # Testcase 116 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest116 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest116: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend116: + + csrrw x0, mtvec, x31 + sd x25, 928(x6) +sd x15, 936(x6) + + # Testcase 118 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest118 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest118: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend118: + + csrrw x0, mtvec, x31 + sd x25, 944(x6) +sd x15, 952(x6) + + # Testcase 120 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest120 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest120: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 20 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend120: + + csrrw x0, mtvec, x31 + sd x25, 960(x6) +sd x15, 968(x6) + + # Testcase 122 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest122 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest122: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 20 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend122: + + csrrw x0, mtvec, x31 + sd x25, 976(x6) +sd x15, 984(x6) + + # Testcase 124 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest124 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest124: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend124: + + csrrw x0, mtvec, x31 + sd x25, 992(x6) +sd x15, 1000(x6) + + # Testcase 126 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest126 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest126: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 30 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend126: + + csrrw x0, mtvec, x31 + sd x25, 1008(x6) +sd x15, 1016(x6) + + # Testcase 128 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest128 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest128: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend128: + + csrrw x0, mtvec, x31 + sd x25, 1024(x6) +sd x15, 1032(x6) + + # Testcase 130 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest130 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest130: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend130: + + csrrw x0, mtvec, x31 + sd x25, 1040(x6) +sd x15, 1048(x6) + + # Testcase 132 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest132 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest132: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 15 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend132: + + csrrw x0, mtvec, x31 + sd x25, 1056(x6) +sd x15, 1064(x6) + + # Testcase 134 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest134 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest134: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 15 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend134: + + csrrw x0, mtvec, x31 + sd x25, 1072(x6) +sd x15, 1080(x6) + + # Testcase 136 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest136 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest136: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend136: + + csrrw x0, mtvec, x31 + sd x25, 1088(x6) +sd x15, 1096(x6) + + # Testcase 138 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest138 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest138: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 31 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend138: + + csrrw x0, mtvec, x31 + sd x25, 1104(x6) +sd x15, 1112(x6) + + # Testcase 140 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest140 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest140: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend140: + + csrrw x0, mtvec, x31 + sd x25, 1120(x6) +sd x15, 1128(x6) + + # Testcase 142 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest142 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest142: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend142: + + csrrw x0, mtvec, x31 + sd x25, 1136(x6) +sd x15, 1144(x6) + + # Testcase 144 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest144 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest144: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 16 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend144: + + csrrw x0, mtvec, x31 + sd x25, 1152(x6) +sd x15, 1160(x6) + + # Testcase 146 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest146 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest146: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 16 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend146: + + csrrw x0, mtvec, x31 + sd x25, 1168(x6) +sd x15, 1176(x6) + + # Testcase 148 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest148 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest148: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend148: + + csrrw x0, mtvec, x31 + sd x25, 1184(x6) +sd x15, 1192(x6) + + # Testcase 150 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest150 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest150: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 23 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend150: + + csrrw x0, mtvec, x31 + sd x25, 1200(x6) +sd x15, 1208(x6) + + # Testcase 152 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest152 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest152: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend152: + + csrrw x0, mtvec, x31 + sd x25, 1216(x6) +sd x15, 1224(x6) + + # Testcase 154 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest154 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest154: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend154: + + csrrw x0, mtvec, x31 + sd x25, 1232(x6) +sd x15, 1240(x6) + + # Testcase 156 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest156 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest156: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 22 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend156: + + csrrw x0, mtvec, x31 + sd x25, 1248(x6) +sd x15, 1256(x6) + + # Testcase 158 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest158 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest158: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 22 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend158: + + csrrw x0, mtvec, x31 + sd x25, 1264(x6) +sd x15, 1272(x6) + + # Testcase 160 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest160 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest160: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend160: + + csrrw x0, mtvec, x31 + sd x25, 1280(x6) +sd x15, 1288(x6) + + # Testcase 162 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest162 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest162: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 19 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend162: + + csrrw x0, mtvec, x31 + sd x25, 1296(x6) +sd x15, 1304(x6) + + # Testcase 164 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest164 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest164: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend164: + + csrrw x0, mtvec, x31 + sd x25, 1312(x6) +sd x15, 1320(x6) + + # Testcase 166 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest166 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest166: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend166: + + csrrw x0, mtvec, x31 + sd x25, 1328(x6) +sd x15, 1336(x6) + + # Testcase 168 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest168 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest168: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 25 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend168: + + csrrw x0, mtvec, x31 + sd x25, 1344(x6) +sd x15, 1352(x6) + + # Testcase 170 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest170 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest170: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 25 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend170: + + csrrw x0, mtvec, x31 + sd x25, 1360(x6) +sd x15, 1368(x6) + + # Testcase 172 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest172 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest172: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend172: + + csrrw x0, mtvec, x31 + sd x25, 1376(x6) +sd x15, 1384(x6) + + # Testcase 174 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest174 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest174: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 26 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend174: + + csrrw x0, mtvec, x31 + sd x25, 1392(x6) +sd x15, 1400(x6) + + # Testcase 176 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest176 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest176: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend176: + + csrrw x0, mtvec, x31 + sd x25, 1408(x6) +sd x15, 1416(x6) + + # Testcase 178 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest178 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest178: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend178: + + csrrw x0, mtvec, x31 + sd x25, 1424(x6) +sd x15, 1432(x6) + + # Testcase 180 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest180 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest180: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 6 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend180: + + csrrw x0, mtvec, x31 + sd x25, 1440(x6) +sd x15, 1448(x6) + + # Testcase 182 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest182 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest182: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 6 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend182: + + csrrw x0, mtvec, x31 + sd x25, 1456(x6) +sd x15, 1464(x6) + + # Testcase 184 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest184 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest184: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend184: + + csrrw x0, mtvec, x31 + sd x25, 1472(x6) +sd x15, 1480(x6) + + # Testcase 186 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest186 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest186: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 21 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend186: + + csrrw x0, mtvec, x31 + sd x25, 1488(x6) +sd x15, 1496(x6) + + # Testcase 188 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest188 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest188: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend188: + + csrrw x0, mtvec, x31 + sd x25, 1504(x6) +sd x15, 1512(x6) + + # Testcase 190 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest190 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest190: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend190: + + csrrw x0, mtvec, x31 + sd x25, 1520(x6) +sd x15, 1528(x6) + + # Testcase 192 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest192 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest192: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 19 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend192: + + csrrw x0, mtvec, x31 + sd x25, 1536(x6) +sd x15, 1544(x6) + + # Testcase 194 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest194 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest194: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 19 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend194: + + csrrw x0, mtvec, x31 + sd x25, 1552(x6) +sd x15, 1560(x6) + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 196, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S new file mode 100644 index 00000000..c9353e28 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S @@ -0,0 +1,433 @@ +/////////////////////////////////////////// +// +// /imperas-riscv-tests/riscv-test-suite/rv64d/src/WALLY-MSTATUS-rv64d.S +// +// Generated by kmacsaigoren@hmc.edu +// Created on 2021-05-24 13:03:13.519323 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + + + +###################################################################### +# Notes: +# +# The following bitfeilds of mstatus are left untested in this file: +# (as of 25 May 2021) +# +# SXL, UXL (unsupported, hardware depends on XLEN) +# MBE, SBE, UBE (unsupported, endianness is constant) +# TSR, TW, TVM, MXR +# XS (extra extensions not supported) +# MPRV and SUM will be tested as part of the mmu +####################################################################### + + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + +########################### +# Test Code +########################### + +# I sectioned each test into smaller 'functions' with labels to help organize +# and make the code a little more readable + +xs_test: + # test hardwiring of xs to zero + csrr x8, mstatus + li x5, 3 # load mask bits into x5 + slli x5, x5, 15 + jal checkBits + # try to write 11 to xs bits to test hardwiring to zero + li x5, 3 + slli x5, x5, 15 + csrs mstatus, x5 + jal checkBits + + li x7, 1 + slli x7, x7, 5 # mask out F_SUPPORTED bit + csrr x5, misa + and x5, x5, x7 + bnez x5, float_supported + j float_unsupported + + +float_supported: + # *** KMG 6 July 2021: This test DOES NOT satisfactorily test the fs bit, for now it just chekcs that the initial value is zero + # and that it can be written but not much else. + # floating point supported, test, fs, sd bits + li x5, 3 + slli x5, x5, 13 # load fs mask bits into x5 + jal checkBits # should be zero since, even though float is supported, the unit hasn't been turned on *** is this true? + jal checkSD + # force fs to be 11, check SD == 1 + li x5, 3 + slli x5, x5, 13 # load fs mask bits into x5 + csrs mstatus, x5 + jal checkSD + j test_gpio + + +float_unsupported: + # write the same things to memory as if f was supported + + sw x0, 0(x6) # initial FS value is zero + li x5, 0xD5 + sw x5, 4(x6) # sd = 0 + li x5, 0x5D + sw x5, 8(x6) # sd = 1 + addi x6, x6, 12 + + +test_gpio: + # Test MIE bits with GPIO interrupt + # set trap handler for GPIO interrupt + la x5, GPIOTrapHandler + csrw mtvec, x5 + # load interrupt complete flag into x10 + li x10, 0 + # x7 holds 0x6410 if we go through an interrupt and 0x0146 if not. + li x7, 0x0146 + jal configPLIC + jal configGPIO + # set mie + li x5, 0x800 + csrs mie, x5 + # delegate interrupts to machine mode + li x5, 0xD00 + csrc mideleg, x5 + # set MIE bit + li x5, 8 + csrs mstatus, x5 + # Cause GPIO interrupt + li x5, 0x10060000 + li x28, 0x00080000 + sw x28, 0x0C(x5) + # wait for GPIO interrupt to finish. + 2: beq x0,x10,2b + + + +test_gpio_disabled: + # Test MIE bit with GPIO interrupt + # set trap handler for GPIO interrupt + la x5, GPIOTrapHandler + csrw mtvec, x5 + # load interrupt complete flag into x10 + li x10, 0 + # x7 holds 0x6410 if we go through an interrupt and 0x0146 if not. + li x7, 0x0146 + # clear MIE bit + li x5, 8 + csrc mstatus, x5 + # Cause GPIO interrupt (shouldn't happen) + li x5, 0x10060000 + li x28, 0x00080000 + sw x28, 0x0C(x5) + # Dont need to wait for handler to work since interrupt doesnt happen. + sw x7, 0(x6) + addi x6, x6, 4 + + +priv_stack_testM: + # test the privilege stack using ecall. + # set trap handler(s) + la x5, stackTrapHandlerM + csrw mtvec, x5 + # begin in machine mode. + csrr x28, mstatus + # cause m mode exception. + ecall + + + +priv_stack_testS: + # test the privilege stack using ecall, handling trap in S mode + li x5, 1 + slli x5, x5, 9 # mask out ecall_S_mode for medeleg + csrs medeleg, x5 # delegate traps to S Mode + # set trap handler(s) + la x5, stackTrapHandlerS + csrw stvec, x5 + jal go_supervisor_mode + csrr x28, sstatus + # cause s mode exception. + ecall + + j done + + +######################################### +# Functions/helpers +######################################### + + +checkBits: + # when we load the mask bits into x5, this function stores the masked mstatus to the output + csrr x8, mstatus + and x5, x5, x8 + sw x5, 0(x6) + addi x6, x6, 4 + li x5, 0 + ret + +checkBitsS: + # same as checkbits, but checks the sstatus csr + csrr x8, sstatus + and x5, x5, x8 + sw x5, 0(x6) + addi x6, x6, 4 + li x5, 0 + ret + + +checkSD: + # checks SD specially because its the first bit, so we don't have to mask. + csrr x8, mstatus + li x5, 0x5D # SD == 1 + bltz x8, sdDirty + li x5, 0xD5 # SD == 0 +sdDirty: + sw x5, 0(x6) + addi x6, x6, 4 + ret + + + + +go_supervisor_mode: + # taken from wally final report spr 2021 + li x28, 3 + slli x28, x28, 11 + csrc mstatus, x28 # clear bits 11 and 12 of mstatus + li x28, 1 + slli x28, x28, 11 + csrs mstatus, x28 # Set bits 11 and 12 of mstatus to 01, meaning + # the previous privilege mode is supervisor mode + auipc x28, 0 # Store the current program counter address in x28 + addi x28, x28, 16 # x28 is now right after the mret instruction + csrw mepc, x28 # Set mepc to the value in x28 + mret # On mret, we go back to the previous privilege mode in + # mstatus (S) and go to the next instruction. + ret # after going into supervisor mode, we need to return from this function + + +configPLIC: + + # priority threshold = 0 + li x5, 0xC200000 + li x28, 0 + sw x28, 0(x5) + # source 3 (GPIO) priority = 6 + li x5, 0xC000000 + li x28, 6 + sw x28, 0x0C(x5) + # source 4 (UART) priority = 7 + li x28, 7 + sw x28, 0x10(x5) + # enable sources 3,4 + li x5, 0x0C002000 + li x28, 0b11000 + sw x28, 0(x5) + ret + + + +configGPIO: + + # enable all inputs + li x5, 0x10060000 + li x28, 0xFFFFFFFF + sw x28, 0x04(x5) + # enable all outputs + sw x28, 0x08(x5) + # enable all rising edge interrupts + sw x28, 0x18(x5) + # set MEIE + li x5, 0x800 + csrs mie, x5 + ret + + +stackTrapHandlerM: + # trap handler for when we use ecall to test the privilege mode stack. + # x28 holds the previous mstatus value + csrr x29, mstatus + li x5, 3 + slli x5, x5, 11 # mask out MPP bits + jal checkBits # mpp should be 11 + + li x5, 1 + slli x5, x5, 8 # mask out spp bits + jal checkBits # spp should be zero. + + li x5, 1 + slli x5, x5, 3 # mask out MIE bit + jal checkBits # MIE should be set to zero + + li x5, 1 + slli x5, x5, 7 # mask out MPIE bit + and x5, x29, x5 + li x7, 1 + slli x7, x7, 3 # mask out previous MIE bit + and x7, x7, x28 + slli x7, x7, 4 # put the bits in the same place + xor x5, x7, x5 # check if theyre the same + sw x5, 0(x6) # should be all zeros. + addi x6, x6, 4 + + li x5, 1 + slli x5, x5, 5 # mask out SPIE bit + and x5, x29, x5 + li x7, 2 # mask out previous SIE bit + and x7, x7, x28 + slli x7, x7, 4 # put the bits in the same place + xor x5, x7, x5 # check if theyre the same + sw x5, 0(x6) # should be all zeros. + addi x6, x6, 4 + + csrr x29, mepc + addi x29, x29, 4 + csrw mepc, x29 + + mret + +stackTrapHandlerS: + # trap handler for when we use ecall to test the privilege mode stack. + # x28 holds the previous sstatus value + csrr x29, sstatus + + li x5, 1 + slli x5, x5, 8 # mask out spp bit + jal checkBitsS # spp should be 1. + + + li x5, 1 + slli x5, x5, 1 # mask out SIE bit + jal checkBitsS # SIE should be set to zero + + li x5, 1 + slli x5, x5, 5 # mask out SPIE bit + and x5, x29, x5 + li x7, 2 # mask out previous SIE bit + and x7, x7, x28 + slli x7, x7, 4 # put the bits in the same place + xor x5, x7, x5 # check if theyre the same + sw x5, 0(x6) # should be all zeros. + addi x6, x6, 4 + + # set return location to AFTER the ecall. + csrr x29, sepc + addi x29, x29, 4 + csrw sepc, x29 + + sret + + + + +GPIOTrapHandler: + + # several 'set low' reads to indicate we've handled the interrupt. + # 0x10: input_val + li x5, 0x10060000 + lw x7, 0x00(x5) + # 0x14: output_val + lw x7, 0x0C(x5) + # 0x18: incoming rise_ip + lw x7, 0x1C(x5) + # 0x1C: serviced rise_ip = 0 + sw x7, 0x1C(x5) + lw x7, 0x1C(x5) + # 0x20: incoming fall_ip + lw x7, 0x24(x5) + # 0x24: serviced fall_ip = 0 + sw x7, 0x24(x5) + lw x7, 0x24(x5) + # 0x28: incoming high_ip + lw x7, 0x2C(x5) + # 0x2C: serviced high_ip = 0 + sw x7, 0x2C(x5) + lw x7, 0x2C(x5) + # 0x30: incoming low_ip + lw x7, 0x34(x5) + + # 0x34: serviced low_ip = 0 + sw x7, 0x34(x5) + lw x7, 0x34(x5) + + + # check PLIC claim register + # (has the side effect of telling the PLIC that this interrupt is being handled) + li x5, 0x0C200004 + lw x7, 0(x5) + + # skip a lot of the GPIO handling because this test doesnt care about the actual input + # and receiving the value from GPIO, we just care about whther the interrupt happened. + li x7, 0x6410 # "gpio" + sw x7, 0(x6) + addi x6, x6, 4 + + # Signal to PLIC that the trap was handled. + li x5, 0x0C200004 + li x7, 3 + sw x7, 0(x5) + + # reset GPIO, show interrupt was handled + li x5, 0x10060000 + li x28, 0x00080000 + sw x28, 0x1C(x5) + + + li x10, 0x76 # random nonzero number to break the bne x0 loop + mret + +done: +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 16, 4, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S new file mode 100644 index 00000000..cef87b73 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S @@ -0,0 +1,1455 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MTVEC.S +// dottolia@hmc.edu +// Created 2021-06-15 11:28:06.476830// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + csrr x19, mtvec + + + li x1, 2 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 0(x6) + + + li x1, 3 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 8(x6) + + + li x1, 2 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 16(x6) + + + li x1, 3 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 24(x6) + + + li x1, 6 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 32(x6) + + + li x1, 7 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 40(x6) + + + li x1, 6 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 48(x6) + + + li x1, 7 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 56(x6) + + + li x1, 10 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 64(x6) + + + li x1, 11 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 72(x6) + + + li x1, 10 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 80(x6) + + + li x1, 11 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 88(x6) + + + li x1, 14 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 96(x6) + + + li x1, 15 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 104(x6) + + + li x1, 14 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 112(x6) + + + li x1, 15 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 120(x6) + + csrw mtvec, x19 + + # add x7, x6, x0 + csrr x19, mtvec + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak_True + + # Machine mode traps + _j_m_trap_ebreak_True: + + nop + nop + li x25, 0 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 1 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 2 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 3 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 4 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 5 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 6 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 7 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 8 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 9 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 10 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 11 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 12 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 13 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 14 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 15 + j _j_m_trap_end_ebreak_True + + + _j_m_trap_end_ebreak_True: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak_True + mret + + # Supervisor mode traps + _j_s_trap_ebreak_True: + + nop + nop + li x25, 0 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 1 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 2 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 3 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 4 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 5 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 6 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 7 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 8 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 9 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 10 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 11 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 12 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 13 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 14 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 15 + j _j_s_trap_end_ebreak_True + + + _j_s_trap_end_ebreak_True: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak_True + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak_True: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak_True + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak_True: + j _j_goto_machine_mode_ebreak_True + + _j_goto_machine_mode_ebreak_True: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak_True in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak_True: + + csrr x18, medeleg + li x9, 0 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0 + csrw mideleg, x9 + + + la x28, _jtest16 + j _jdo16 + + _jtest16: + nop + + jr x27 + + _jdo16: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 128(x6) + + + la x28, _jtest17 + j _jdo17 + + _jtest17: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo17: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 136(x6) + + + la x28, _jtest18 + j _jdo18 + + _jtest18: + nop + + jr x27 + + _jdo18: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 144(x6) + + + la x28, _jtest19 + j _jdo19 + + _jtest19: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo19: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 152(x6) + + + la x28, _jtest20 + j _jdo20 + + _jtest20: + nop + + jr x27 + + _jdo20: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 160(x6) + + + la x28, _jtest21 + j _jdo21 + + _jtest21: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo21: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 168(x6) + + + la x28, _jtest22 + j _jdo22 + + _jtest22: + nop + + jr x27 + + _jdo22: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 176(x6) + + + la x28, _jtest23 + j _jdo23 + + _jtest23: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo23: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 184(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + la x28, _jtest24 + j _jdo24 + + _jtest24: + nop + + jr x27 + + _jdo24: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 192(x6) + + + la x28, _jtest25 + j _jdo25 + + _jtest25: + nop + + jr x27 + + _jdo25: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 200(x6) + + + la x28, _jtest26 + j _jdo26 + + _jtest26: + nop + + jr x27 + + _jdo26: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 208(x6) + + + la x28, _jtest27 + j _jdo27 + + _jtest27: + nop + + jr x27 + + _jdo27: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 216(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + + la x28, _jtest28 + j _jdo28 + + _jtest28: + nop + + jr x27 + + _jdo28: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 224(x6) + + + la x28, _jtest29 + j _jdo29 + + _jtest29: + nop + + jr x27 + + _jdo29: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 232(x6) + + + la x28, _jtest30 + j _jdo30 + + _jtest30: + nop + + jr x27 + + _jdo30: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 240(x6) + + + la x28, _jtest31 + j _jdo31 + + _jtest31: + nop + + jr x27 + + _jdo31: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 248(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak_True: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + + # add x7, x6, x0 + csrr x19, mtvec + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak_False + # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_ebreak_False + # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_ebreak_False + # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak_False + + # Machine mode traps + _j_m_trap_ebreak_False: + + nop + nop + li x25, 0 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 1 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 2 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 3 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 4 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 5 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 6 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 7 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 8 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 9 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 10 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 11 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 12 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 13 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 14 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 15 + j _j_m_trap_end_ebreak_False + + + _j_m_trap_end_ebreak_False: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak_False + mret + + # Supervisor mode traps + _j_s_trap_ebreak_False: + + nop + nop + li x25, 0 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 1 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 2 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 3 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 4 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 5 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 6 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 7 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 8 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 9 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 10 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 11 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 12 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 13 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 14 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 15 + j _j_s_trap_end_ebreak_False + + + _j_s_trap_end_ebreak_False: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak_False + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak_False: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak_False + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak_False: + j _j_goto_machine_mode_ebreak_False + + _j_goto_machine_mode_ebreak_False: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak_False in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak_False: + + csrr x18, medeleg + li x9, 0 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0 + csrw mideleg, x9 + + + la x28, _jtest32 + j _jdo32 + + _jtest32: + nop + + jr x27 + + _jdo32: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 256(x6) + + + la x28, _jtest33 + j _jdo33 + + _jtest33: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo33: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 264(x6) + + + la x28, _jtest34 + j _jdo34 + + _jtest34: + nop + + jr x27 + + _jdo34: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 272(x6) + + + la x28, _jtest35 + j _jdo35 + + _jtest35: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo35: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 280(x6) + + + la x28, _jtest36 + j _jdo36 + + _jtest36: + nop + + jr x27 + + _jdo36: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 288(x6) + + + la x28, _jtest37 + j _jdo37 + + _jtest37: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo37: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 296(x6) + + + la x28, _jtest38 + j _jdo38 + + _jtest38: + nop + + jr x27 + + _jdo38: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 304(x6) + + + la x28, _jtest39 + j _jdo39 + + _jtest39: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo39: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 312(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + la x28, _jtest40 + j _jdo40 + + _jtest40: + nop + + jr x27 + + _jdo40: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 320(x6) + + + la x28, _jtest41 + j _jdo41 + + _jtest41: + nop + + jr x27 + + _jdo41: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 328(x6) + + + la x28, _jtest42 + j _jdo42 + + _jtest42: + nop + + jr x27 + + _jdo42: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 336(x6) + + + la x28, _jtest43 + j _jdo43 + + _jtest43: + nop + + jr x27 + + _jdo43: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 344(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + + la x28, _jtest44 + j _jdo44 + + _jtest44: + nop + + jr x27 + + _jdo44: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 352(x6) + + + la x28, _jtest45 + j _jdo45 + + _jtest45: + nop + + jr x27 + + _jdo45: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 360(x6) + + + la x28, _jtest46 + j _jdo46 + + _jtest46: + nop + + jr x27 + + _jdo46: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 368(x6) + + + la x28, _jtest47 + j _jdo47 + + _jtest47: + nop + + jr x27 + + _jdo47: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 376(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak_False: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 48, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S new file mode 100644 index 00000000..88578124 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S @@ -0,0 +1,3778 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MVENDORID.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:52.370113// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + # Testcase 0 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest0 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest0: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend0: + + csrrw x0, mtvec, x31 + sd x25, 0(x6) +sd x15, 8(x6) + + # Testcase 2 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest2 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest2: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 0 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend2: + + csrrw x0, mtvec, x31 + sd x25, 16(x6) +sd x15, 24(x6) + + # Testcase 4 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest4 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest4: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend4: + + csrrw x0, mtvec, x31 + sd x25, 32(x6) +sd x15, 40(x6) + + # Testcase 6 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest6 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest6: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend6: + + csrrw x0, mtvec, x31 + sd x25, 48(x6) +sd x15, 56(x6) + + # Testcase 8 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest8 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest8: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend8: + + csrrw x0, mtvec, x31 + sd x25, 64(x6) +sd x15, 72(x6) + + # Testcase 10 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest10 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest10: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend10: + + csrrw x0, mtvec, x31 + sd x25, 80(x6) +sd x15, 88(x6) + + # Testcase 12 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest12 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest12: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend12: + + csrrw x0, mtvec, x31 + sd x25, 96(x6) +sd x15, 104(x6) + + # Testcase 14 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest14 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest14: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend14: + + csrrw x0, mtvec, x31 + sd x25, 112(x6) +sd x15, 120(x6) + + # Testcase 16 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest16 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest16: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend16: + + csrrw x0, mtvec, x31 + sd x25, 128(x6) +sd x15, 136(x6) + + # Testcase 18 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest18 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest18: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend18: + + csrrw x0, mtvec, x31 + sd x25, 144(x6) +sd x15, 152(x6) + + # Testcase 20 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest20 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest20: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend20: + + csrrw x0, mtvec, x31 + sd x25, 160(x6) +sd x15, 168(x6) + + # Testcase 22 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest22 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest22: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend22: + + csrrw x0, mtvec, x31 + sd x25, 176(x6) +sd x15, 184(x6) + + # Testcase 24 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest24 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest24: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 3 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend24: + + csrrw x0, mtvec, x31 + sd x25, 192(x6) +sd x15, 200(x6) + + # Testcase 26 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest26 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest26: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 3 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend26: + + csrrw x0, mtvec, x31 + sd x25, 208(x6) +sd x15, 216(x6) + + # Testcase 28 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest28 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest28: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend28: + + csrrw x0, mtvec, x31 + sd x25, 224(x6) +sd x15, 232(x6) + + # Testcase 30 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest30 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest30: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 31 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend30: + + csrrw x0, mtvec, x31 + sd x25, 240(x6) +sd x15, 248(x6) + + # Testcase 32 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest32 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest32: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend32: + + csrrw x0, mtvec, x31 + sd x25, 256(x6) +sd x15, 264(x6) + + # Testcase 34 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest34 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest34: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend34: + + csrrw x0, mtvec, x31 + sd x25, 272(x6) +sd x15, 280(x6) + + # Testcase 36 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest36 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest36: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend36: + + csrrw x0, mtvec, x31 + sd x25, 288(x6) +sd x15, 296(x6) + + # Testcase 38 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest38 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest38: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend38: + + csrrw x0, mtvec, x31 + sd x25, 304(x6) +sd x15, 312(x6) + + # Testcase 40 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest40 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest40: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend40: + + csrrw x0, mtvec, x31 + sd x25, 320(x6) +sd x15, 328(x6) + + # Testcase 42 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest42 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest42: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 0 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend42: + + csrrw x0, mtvec, x31 + sd x25, 336(x6) +sd x15, 344(x6) + + # Testcase 44 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest44 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest44: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend44: + + csrrw x0, mtvec, x31 + sd x25, 352(x6) +sd x15, 360(x6) + + # Testcase 46 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest46 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest46: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend46: + + csrrw x0, mtvec, x31 + sd x25, 368(x6) +sd x15, 376(x6) + + # Testcase 48 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest48 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest48: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend48: + + csrrw x0, mtvec, x31 + sd x25, 384(x6) +sd x15, 392(x6) + + # Testcase 50 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest50 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest50: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend50: + + csrrw x0, mtvec, x31 + sd x25, 400(x6) +sd x15, 408(x6) + + # Testcase 52 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest52 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest52: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend52: + + csrrw x0, mtvec, x31 + sd x25, 416(x6) +sd x15, 424(x6) + + # Testcase 54 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest54 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest54: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 20 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend54: + + csrrw x0, mtvec, x31 + sd x25, 432(x6) +sd x15, 440(x6) + + # Testcase 56 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest56 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest56: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend56: + + csrrw x0, mtvec, x31 + sd x25, 448(x6) +sd x15, 456(x6) + + # Testcase 58 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest58 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest58: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend58: + + csrrw x0, mtvec, x31 + sd x25, 464(x6) +sd x15, 472(x6) + + # Testcase 60 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest60 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest60: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 28 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend60: + + csrrw x0, mtvec, x31 + sd x25, 480(x6) +sd x15, 488(x6) + + # Testcase 62 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest62 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest62: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 28 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend62: + + csrrw x0, mtvec, x31 + sd x25, 496(x6) +sd x15, 504(x6) + + # Testcase 64 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest64 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest64: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend64: + + csrrw x0, mtvec, x31 + sd x25, 512(x6) +sd x15, 520(x6) + + # Testcase 66 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest66 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest66: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 30 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend66: + + csrrw x0, mtvec, x31 + sd x25, 528(x6) +sd x15, 536(x6) + + # Testcase 68 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest68 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest68: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend68: + + csrrw x0, mtvec, x31 + sd x25, 544(x6) +sd x15, 552(x6) + + # Testcase 70 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest70 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest70: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend70: + + csrrw x0, mtvec, x31 + sd x25, 560(x6) +sd x15, 568(x6) + + # Testcase 72 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest72 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest72: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 7 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend72: + + csrrw x0, mtvec, x31 + sd x25, 576(x6) +sd x15, 584(x6) + + # Testcase 74 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest74 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest74: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 7 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend74: + + csrrw x0, mtvec, x31 + sd x25, 592(x6) +sd x15, 600(x6) + + # Testcase 76 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest76 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest76: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend76: + + csrrw x0, mtvec, x31 + sd x25, 608(x6) +sd x15, 616(x6) + + # Testcase 78 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest78 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest78: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 31 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend78: + + csrrw x0, mtvec, x31 + sd x25, 624(x6) +sd x15, 632(x6) + + # Testcase 80 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest80 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest80: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend80: + + csrrw x0, mtvec, x31 + sd x25, 640(x6) +sd x15, 648(x6) + + # Testcase 82 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest82 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest82: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend82: + + csrrw x0, mtvec, x31 + sd x25, 656(x6) +sd x15, 664(x6) + + # Testcase 84 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest84 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest84: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 8 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend84: + + csrrw x0, mtvec, x31 + sd x25, 672(x6) +sd x15, 680(x6) + + # Testcase 86 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest86 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest86: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 8 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend86: + + csrrw x0, mtvec, x31 + sd x25, 688(x6) +sd x15, 696(x6) + + # Testcase 88 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest88 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest88: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend88: + + csrrw x0, mtvec, x31 + sd x25, 704(x6) +sd x15, 712(x6) + + # Testcase 90 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest90 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest90: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 0 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend90: + + csrrw x0, mtvec, x31 + sd x25, 720(x6) +sd x15, 728(x6) + + # Testcase 92 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest92 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest92: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend92: + + csrrw x0, mtvec, x31 + sd x25, 736(x6) +sd x15, 744(x6) + + # Testcase 94 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest94 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest94: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend94: + + csrrw x0, mtvec, x31 + sd x25, 752(x6) +sd x15, 760(x6) + + # Testcase 96 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest96 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest96: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 9 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend96: + + csrrw x0, mtvec, x31 + sd x25, 768(x6) +sd x15, 776(x6) + + # Testcase 98 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest98 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest98: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 9 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend98: + + csrrw x0, mtvec, x31 + sd x25, 784(x6) +sd x15, 792(x6) + + # Testcase 100 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest100 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest100: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend100: + + csrrw x0, mtvec, x31 + sd x25, 800(x6) +sd x15, 808(x6) + + # Testcase 102 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest102 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest102: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend102: + + csrrw x0, mtvec, x31 + sd x25, 816(x6) +sd x15, 824(x6) + + # Testcase 104 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest104 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest104: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend104: + + csrrw x0, mtvec, x31 + sd x25, 832(x6) +sd x15, 840(x6) + + # Testcase 106 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest106 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest106: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend106: + + csrrw x0, mtvec, x31 + sd x25, 848(x6) +sd x15, 856(x6) + + # Testcase 108 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest108 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest108: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 10 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend108: + + csrrw x0, mtvec, x31 + sd x25, 864(x6) +sd x15, 872(x6) + + # Testcase 110 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest110 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest110: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 10 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend110: + + csrrw x0, mtvec, x31 + sd x25, 880(x6) +sd x15, 888(x6) + + # Testcase 112 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest112 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest112: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend112: + + csrrw x0, mtvec, x31 + sd x25, 896(x6) +sd x15, 904(x6) + + # Testcase 114 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest114 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest114: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend114: + + csrrw x0, mtvec, x31 + sd x25, 912(x6) +sd x15, 920(x6) + + # Testcase 116 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest116 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest116: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend116: + + csrrw x0, mtvec, x31 + sd x25, 928(x6) +sd x15, 936(x6) + + # Testcase 118 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest118 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest118: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend118: + + csrrw x0, mtvec, x31 + sd x25, 944(x6) +sd x15, 952(x6) + + # Testcase 120 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest120 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest120: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 20 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend120: + + csrrw x0, mtvec, x31 + sd x25, 960(x6) +sd x15, 968(x6) + + # Testcase 122 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest122 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest122: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 20 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend122: + + csrrw x0, mtvec, x31 + sd x25, 976(x6) +sd x15, 984(x6) + + # Testcase 124 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest124 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest124: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend124: + + csrrw x0, mtvec, x31 + sd x25, 992(x6) +sd x15, 1000(x6) + + # Testcase 126 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest126 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest126: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 30 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend126: + + csrrw x0, mtvec, x31 + sd x25, 1008(x6) +sd x15, 1016(x6) + + # Testcase 128 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest128 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest128: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend128: + + csrrw x0, mtvec, x31 + sd x25, 1024(x6) +sd x15, 1032(x6) + + # Testcase 130 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest130 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest130: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend130: + + csrrw x0, mtvec, x31 + sd x25, 1040(x6) +sd x15, 1048(x6) + + # Testcase 132 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest132 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest132: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 15 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend132: + + csrrw x0, mtvec, x31 + sd x25, 1056(x6) +sd x15, 1064(x6) + + # Testcase 134 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest134 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest134: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 15 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend134: + + csrrw x0, mtvec, x31 + sd x25, 1072(x6) +sd x15, 1080(x6) + + # Testcase 136 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest136 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest136: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend136: + + csrrw x0, mtvec, x31 + sd x25, 1088(x6) +sd x15, 1096(x6) + + # Testcase 138 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest138 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest138: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 31 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend138: + + csrrw x0, mtvec, x31 + sd x25, 1104(x6) +sd x15, 1112(x6) + + # Testcase 140 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest140 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest140: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend140: + + csrrw x0, mtvec, x31 + sd x25, 1120(x6) +sd x15, 1128(x6) + + # Testcase 142 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest142 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest142: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend142: + + csrrw x0, mtvec, x31 + sd x25, 1136(x6) +sd x15, 1144(x6) + + # Testcase 144 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest144 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest144: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 16 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend144: + + csrrw x0, mtvec, x31 + sd x25, 1152(x6) +sd x15, 1160(x6) + + # Testcase 146 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest146 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest146: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 16 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend146: + + csrrw x0, mtvec, x31 + sd x25, 1168(x6) +sd x15, 1176(x6) + + # Testcase 148 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest148 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest148: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend148: + + csrrw x0, mtvec, x31 + sd x25, 1184(x6) +sd x15, 1192(x6) + + # Testcase 150 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest150 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest150: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 10 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend150: + + csrrw x0, mtvec, x31 + sd x25, 1200(x6) +sd x15, 1208(x6) + + # Testcase 152 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest152 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest152: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend152: + + csrrw x0, mtvec, x31 + sd x25, 1216(x6) +sd x15, 1224(x6) + + # Testcase 154 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest154 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest154: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend154: + + csrrw x0, mtvec, x31 + sd x25, 1232(x6) +sd x15, 1240(x6) + + # Testcase 156 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest156 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest156: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 18 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend156: + + csrrw x0, mtvec, x31 + sd x25, 1248(x6) +sd x15, 1256(x6) + + # Testcase 158 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest158 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest158: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 18 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend158: + + csrrw x0, mtvec, x31 + sd x25, 1264(x6) +sd x15, 1272(x6) + + # Testcase 160 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest160 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest160: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend160: + + csrrw x0, mtvec, x31 + sd x25, 1280(x6) +sd x15, 1288(x6) + + # Testcase 162 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest162 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest162: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 14 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend162: + + csrrw x0, mtvec, x31 + sd x25, 1296(x6) +sd x15, 1304(x6) + + # Testcase 164 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest164 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest164: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend164: + + csrrw x0, mtvec, x31 + sd x25, 1312(x6) +sd x15, 1320(x6) + + # Testcase 166 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest166 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest166: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend166: + + csrrw x0, mtvec, x31 + sd x25, 1328(x6) +sd x15, 1336(x6) + + # Testcase 168 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest168 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest168: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 16 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend168: + + csrrw x0, mtvec, x31 + sd x25, 1344(x6) +sd x15, 1352(x6) + + # Testcase 170 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest170 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest170: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 16 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend170: + + csrrw x0, mtvec, x31 + sd x25, 1360(x6) +sd x15, 1368(x6) + + # Testcase 172 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest172 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest172: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend172: + + csrrw x0, mtvec, x31 + sd x25, 1376(x6) +sd x15, 1384(x6) + + # Testcase 174 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest174 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest174: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 25 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend174: + + csrrw x0, mtvec, x31 + sd x25, 1392(x6) +sd x15, 1400(x6) + + # Testcase 176 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest176 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest176: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend176: + + csrrw x0, mtvec, x31 + sd x25, 1408(x6) +sd x15, 1416(x6) + + # Testcase 178 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest178 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest178: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend178: + + csrrw x0, mtvec, x31 + sd x25, 1424(x6) +sd x15, 1432(x6) + + # Testcase 180 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest180 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest180: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 23 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend180: + + csrrw x0, mtvec, x31 + sd x25, 1440(x6) +sd x15, 1448(x6) + + # Testcase 182 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest182 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest182: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 23 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend182: + + csrrw x0, mtvec, x31 + sd x25, 1456(x6) +sd x15, 1464(x6) + + # Testcase 184 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest184 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest184: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend184: + + csrrw x0, mtvec, x31 + sd x25, 1472(x6) +sd x15, 1480(x6) + + # Testcase 186 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest186 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest186: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend186: + + csrrw x0, mtvec, x31 + sd x25, 1488(x6) +sd x15, 1496(x6) + + # Testcase 188 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest188 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest188: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend188: + + csrrw x0, mtvec, x31 + sd x25, 1504(x6) +sd x15, 1512(x6) + + # Testcase 190 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest190 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest190: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend190: + + csrrw x0, mtvec, x31 + sd x25, 1520(x6) +sd x15, 1528(x6) + + # Testcase 192 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest192 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest192: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend192: + + csrrw x0, mtvec, x31 + sd x25, 1536(x6) +sd x15, 1544(x6) + + # Testcase 194 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest194 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest194: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend194: + + csrrw x0, mtvec, x31 + sd x25, 1552(x6) +sd x15, 1560(x6) + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 196, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S new file mode 100644 index 00000000..d509ae89 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S @@ -0,0 +1,1396 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-SCAUSE.S +// dottolia@hmc.edu +// Created 2021-06-16 16:18:36.397499// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + + slli a0,a0,0x1f + slli a0,a0,0x1e + slli a0,a0,0x1d + slli a0,a0,0x1c + slli a0,a0,0x1b + slli a0,a0,0x1a + slli a0,a0,0x19 + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak + csrw mtvec, x1 + la x1, _j_s_trap_ebreak + csrw stvec, x1 + la x1, _j_u_trap_ebreak + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak + + # Machine mode traps + _j_m_trap_ebreak: + li x25, 0xBAD00003 + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak + mret + + # Supervisor mode traps + _j_s_trap_ebreak: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak: + j _j_goto_machine_mode_ebreak + + _j_goto_machine_mode_ebreak: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak: + + csrr x18, medeleg + li x9, 0b1111111111110111 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0xffffffff + csrw mideleg, x9 + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + la x28, _jtest0 + j _jdo0 + + _jtest0: + + csrr x25, scause + + + jr x27 + + _jdo0: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 0(x6) + + la x28, _jtest1 + j _jdo1 + + _jtest1: + + csrr x25, scause + + + jr x27 + + _jdo1: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 8(x6) + + la x28, _jtest2 + j _jdo2 + + _jtest2: + + csrr x25, scause + + + jr x27 + + _jdo2: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 16(x6) + + la x28, _jtest3 + j _jdo3 + + _jtest3: + + csrr x25, scause + + + jr x27 + + _jdo3: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 24(x6) + + la x28, _jtest4 + j _jdo4 + + _jtest4: + + csrr x25, scause + + + jr x27 + + _jdo4: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 32(x6) + + la x28, _jtest5 + j _jdo5 + + _jtest5: + + csrr x25, scause + + + jr x27 + + _jdo5: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 40(x6) + + la x28, _jtest6 + j _jdo6 + + _jtest6: + + csrr x25, scause + + + jr x27 + + _jdo6: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 48(x6) + + la x28, _jtest7 + j _jdo7 + + _jtest7: + + csrr x25, scause + + + jr x27 + + _jdo7: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 56(x6) + + la x28, _jtest8 + j _jdo8 + + _jtest8: + + csrr x25, scause + + + jr x27 + + _jdo8: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 64(x6) + + la x28, _jtest9 + j _jdo9 + + _jtest9: + + csrr x25, scause + + + jr x27 + + _jdo9: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 72(x6) + + la x28, _jtest10 + j _jdo10 + + _jtest10: + + csrr x25, scause + + + jr x27 + + _jdo10: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 80(x6) + + la x28, _jtest11 + j _jdo11 + + _jtest11: + + csrr x25, scause + + + jr x27 + + _jdo11: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 88(x6) + + la x28, _jtest12 + j _jdo12 + + _jtest12: + + csrr x25, scause + + + jr x27 + + _jdo12: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 96(x6) + + la x28, _jtest13 + j _jdo13 + + _jtest13: + + csrr x25, scause + + + jr x27 + + _jdo13: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 104(x6) + + la x28, _jtest14 + j _jdo14 + + _jtest14: + + csrr x25, scause + + + jr x27 + + _jdo14: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 112(x6) + + la x28, _jtest15 + j _jdo15 + + _jtest15: + + csrr x25, scause + + + jr x27 + + _jdo15: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 120(x6) + + la x28, _jtest16 + j _jdo16 + + _jtest16: + + csrr x25, scause + + + jr x27 + + _jdo16: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 128(x6) + + la x28, _jtest17 + j _jdo17 + + _jtest17: + + csrr x25, scause + + + jr x27 + + _jdo17: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 136(x6) + + la x28, _jtest18 + j _jdo18 + + _jtest18: + + csrr x25, scause + + + jr x27 + + _jdo18: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 144(x6) + + la x28, _jtest19 + j _jdo19 + + _jtest19: + + csrr x25, scause + + + jr x27 + + _jdo19: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 152(x6) + + la x28, _jtest20 + j _jdo20 + + _jtest20: + + csrr x25, scause + + + jr x27 + + _jdo20: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 160(x6) + + la x28, _jtest21 + j _jdo21 + + _jtest21: + + csrr x25, scause + + + jr x27 + + _jdo21: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 168(x6) + + la x28, _jtest22 + j _jdo22 + + _jtest22: + + csrr x25, scause + + + jr x27 + + _jdo22: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 176(x6) + + la x28, _jtest23 + j _jdo23 + + _jtest23: + + csrr x25, scause + + + jr x27 + + _jdo23: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 184(x6) + + la x28, _jtest24 + j _jdo24 + + _jtest24: + + csrr x25, scause + + + jr x27 + + _jdo24: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 192(x6) + + la x28, _jtest25 + j _jdo25 + + _jtest25: + + csrr x25, scause + + + jr x27 + + _jdo25: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 200(x6) + + la x28, _jtest26 + j _jdo26 + + _jtest26: + + csrr x25, scause + + + jr x27 + + _jdo26: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 208(x6) + + la x28, _jtest27 + j _jdo27 + + _jtest27: + + csrr x25, scause + + + jr x27 + + _jdo27: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 216(x6) + + la x28, _jtest28 + j _jdo28 + + _jtest28: + + csrr x25, scause + + + jr x27 + + _jdo28: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 224(x6) + + la x28, _jtest29 + j _jdo29 + + _jtest29: + + csrr x25, scause + + + jr x27 + + _jdo29: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 232(x6) + + la x28, _jtest30 + j _jdo30 + + _jtest30: + + csrr x25, scause + + + jr x27 + + _jdo30: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 240(x6) + + la x28, _jtest31 + j _jdo31 + + _jtest31: + + csrr x25, scause + + + jr x27 + + _jdo31: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 248(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + la x28, _jtest32 + j _jdo32 + + _jtest32: + + csrr x25, scause + + + jr x27 + + _jdo32: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 256(x6) + + la x28, _jtest33 + j _jdo33 + + _jtest33: + + csrr x25, scause + + + jr x27 + + _jdo33: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 264(x6) + + la x28, _jtest34 + j _jdo34 + + _jtest34: + + csrr x25, scause + + + jr x27 + + _jdo34: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 272(x6) + + la x28, _jtest35 + j _jdo35 + + _jtest35: + + csrr x25, scause + + + jr x27 + + _jdo35: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 280(x6) + + la x28, _jtest36 + j _jdo36 + + _jtest36: + + csrr x25, scause + + + jr x27 + + _jdo36: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 288(x6) + + la x28, _jtest37 + j _jdo37 + + _jtest37: + + csrr x25, scause + + + jr x27 + + _jdo37: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 296(x6) + + la x28, _jtest38 + j _jdo38 + + _jtest38: + + csrr x25, scause + + + jr x27 + + _jdo38: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 304(x6) + + la x28, _jtest39 + j _jdo39 + + _jtest39: + + csrr x25, scause + + + jr x27 + + _jdo39: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 312(x6) + + la x28, _jtest40 + j _jdo40 + + _jtest40: + + csrr x25, scause + + + jr x27 + + _jdo40: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 320(x6) + + la x28, _jtest41 + j _jdo41 + + _jtest41: + + csrr x25, scause + + + jr x27 + + _jdo41: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 328(x6) + + la x28, _jtest42 + j _jdo42 + + _jtest42: + + csrr x25, scause + + + jr x27 + + _jdo42: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 336(x6) + + la x28, _jtest43 + j _jdo43 + + _jtest43: + + csrr x25, scause + + + jr x27 + + _jdo43: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 344(x6) + + la x28, _jtest44 + j _jdo44 + + _jtest44: + + csrr x25, scause + + + jr x27 + + _jdo44: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 352(x6) + + la x28, _jtest45 + j _jdo45 + + _jtest45: + + csrr x25, scause + + + jr x27 + + _jdo45: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 360(x6) + + la x28, _jtest46 + j _jdo46 + + _jtest46: + + csrr x25, scause + + + jr x27 + + _jdo46: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 368(x6) + + la x28, _jtest47 + j _jdo47 + + _jtest47: + + csrr x25, scause + + + jr x27 + + _jdo47: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 376(x6) + + la x28, _jtest48 + j _jdo48 + + _jtest48: + + csrr x25, scause + + + jr x27 + + _jdo48: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 384(x6) + + la x28, _jtest49 + j _jdo49 + + _jtest49: + + csrr x25, scause + + + jr x27 + + _jdo49: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 392(x6) + + la x28, _jtest50 + j _jdo50 + + _jtest50: + + csrr x25, scause + + + jr x27 + + _jdo50: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 400(x6) + + la x28, _jtest51 + j _jdo51 + + _jtest51: + + csrr x25, scause + + + jr x27 + + _jdo51: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 408(x6) + + la x28, _jtest52 + j _jdo52 + + _jtest52: + + csrr x25, scause + + + jr x27 + + _jdo52: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 416(x6) + + la x28, _jtest53 + j _jdo53 + + _jtest53: + + csrr x25, scause + + + jr x27 + + _jdo53: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 424(x6) + + la x28, _jtest54 + j _jdo54 + + _jtest54: + + csrr x25, scause + + + jr x27 + + _jdo54: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 432(x6) + + la x28, _jtest55 + j _jdo55 + + _jtest55: + + csrr x25, scause + + + jr x27 + + _jdo55: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 440(x6) + + la x28, _jtest56 + j _jdo56 + + _jtest56: + + csrr x25, scause + + + jr x27 + + _jdo56: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 448(x6) + + la x28, _jtest57 + j _jdo57 + + _jtest57: + + csrr x25, scause + + + jr x27 + + _jdo57: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 456(x6) + + la x28, _jtest58 + j _jdo58 + + _jtest58: + + csrr x25, scause + + + jr x27 + + _jdo58: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 464(x6) + + la x28, _jtest59 + j _jdo59 + + _jtest59: + + csrr x25, scause + + + jr x27 + + _jdo59: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 472(x6) + + la x28, _jtest60 + j _jdo60 + + _jtest60: + + csrr x25, scause + + + jr x27 + + _jdo60: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 480(x6) + + la x28, _jtest61 + j _jdo61 + + _jtest61: + + csrr x25, scause + + + jr x27 + + _jdo61: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 488(x6) + + la x28, _jtest62 + j _jdo62 + + _jtest62: + + csrr x25, scause + + + jr x27 + + _jdo62: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 496(x6) + + la x28, _jtest63 + j _jdo63 + + _jtest63: + + csrr x25, scause + + + jr x27 + + _jdo63: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 504(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 64, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S new file mode 100644 index 00000000..4b7fa07e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S @@ -0,0 +1,1022 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-STVEC.S +// dottolia@hmc.edu +// Created 2021-06-15 11:28:06.482303// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + csrr x19, stvec + + + li x1, 2 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 0(x6) + + + li x1, 3 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 8(x6) + + + li x1, 2 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 16(x6) + + + li x1, 3 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 24(x6) + + + li x1, 6 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 32(x6) + + + li x1, 7 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 40(x6) + + + li x1, 6 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 48(x6) + + + li x1, 7 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 56(x6) + + + li x1, 10 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 64(x6) + + + li x1, 11 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 72(x6) + + + li x1, 10 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 80(x6) + + + li x1, 11 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 88(x6) + + + li x1, 14 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 96(x6) + + + li x1, 15 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 104(x6) + + + li x1, 14 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 112(x6) + + + li x1, 15 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 120(x6) + + csrw stvec, x19 + + # add x7, x6, x0 + csrr x19, mtvec + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak_True + + # Machine mode traps + _j_m_trap_ebreak_True: + + nop + nop + li x25, 0 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 1 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 2 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 3 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 4 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 5 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 6 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 7 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 8 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 9 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 10 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 11 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 12 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 13 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 14 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 15 + j _j_m_trap_end_ebreak_True + + + _j_m_trap_end_ebreak_True: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak_True + mret + + # Supervisor mode traps + _j_s_trap_ebreak_True: + + nop + nop + li x25, 0 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 1 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 2 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 3 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 4 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 5 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 6 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 7 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 8 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 9 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 10 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 11 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 12 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 13 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 14 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 15 + j _j_s_trap_end_ebreak_True + + + _j_s_trap_end_ebreak_True: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak_True + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak_True: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak_True + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak_True: + j _j_goto_machine_mode_ebreak_True + + _j_goto_machine_mode_ebreak_True: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak_True in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak_True: + + csrr x18, medeleg + li x9, 0b1111111111110111 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0xffffffff + csrw mideleg, x9 + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + la x28, _jtest16 + j _jdo16 + + _jtest16: + nop + + jr x27 + + _jdo16: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 128(x6) + + + la x28, _jtest17 + j _jdo17 + + _jtest17: + nop + + jr x27 + + _jdo17: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 136(x6) + + + la x28, _jtest18 + j _jdo18 + + _jtest18: + nop + + jr x27 + + _jdo18: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 144(x6) + + + la x28, _jtest19 + j _jdo19 + + _jtest19: + nop + + jr x27 + + _jdo19: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 152(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + + la x28, _jtest20 + j _jdo20 + + _jtest20: + nop + + jr x27 + + _jdo20: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 160(x6) + + + la x28, _jtest21 + j _jdo21 + + _jtest21: + nop + + jr x27 + + _jdo21: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 168(x6) + + + la x28, _jtest22 + j _jdo22 + + _jtest22: + nop + + jr x27 + + _jdo22: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 176(x6) + + + la x28, _jtest23 + j _jdo23 + + _jtest23: + nop + + jr x27 + + _jdo23: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 184(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak_True: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + + # add x7, x6, x0 + csrr x19, mtvec + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak_False + # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_ebreak_False + # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_ebreak_False + # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak_False + + # Machine mode traps + _j_m_trap_ebreak_False: + + nop + nop + li x25, 0 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 1 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 2 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 3 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 4 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 5 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 6 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 7 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 8 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 9 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 10 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 11 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 12 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 13 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 14 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 15 + j _j_m_trap_end_ebreak_False + + + _j_m_trap_end_ebreak_False: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak_False + mret + + # Supervisor mode traps + _j_s_trap_ebreak_False: + + nop + nop + li x25, 0 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 1 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 2 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 3 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 4 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 5 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 6 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 7 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 8 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 9 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 10 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 11 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 12 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 13 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 14 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 15 + j _j_s_trap_end_ebreak_False + + + _j_s_trap_end_ebreak_False: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak_False + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak_False: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak_False + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak_False: + j _j_goto_machine_mode_ebreak_False + + _j_goto_machine_mode_ebreak_False: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak_False in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak_False: + + csrr x18, medeleg + li x9, 0b1111111111110111 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0xffffffff + csrw mideleg, x9 + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + la x28, _jtest24 + j _jdo24 + + _jtest24: + nop + + jr x27 + + _jdo24: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 192(x6) + + + la x28, _jtest25 + j _jdo25 + + _jtest25: + nop + + jr x27 + + _jdo25: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 200(x6) + + + la x28, _jtest26 + j _jdo26 + + _jtest26: + nop + + jr x27 + + _jdo26: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 208(x6) + + + la x28, _jtest27 + j _jdo27 + + _jtest27: + nop + + jr x27 + + _jdo27: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 216(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + + la x28, _jtest28 + j _jdo28 + + _jtest28: + nop + + jr x27 + + _jdo28: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 224(x6) + + + la x28, _jtest29 + j _jdo29 + + _jtest29: + nop + + jr x27 + + _jdo29: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 232(x6) + + + la x28, _jtest30 + j _jdo30 + + _jtest30: + nop + + jr x27 + + _jdo30: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 240(x6) + + + la x28, _jtest31 + j _jdo31 + + _jtest31: + nop + + jr x27 + + _jdo31: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 248(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak_False: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 32, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S new file mode 100644 index 00000000..1d651f57 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S @@ -0,0 +1,459 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-UCAUSE.S +// dottolia@hmc.edu +// Created 2021-04-20 15:11:17.438819// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + csrr x31, mtvec + li x30, 0 + + la x1, _j_m_trap + csrw mtvec, x1 + la x1, _j_s_trap + csrw stvec, x1 + j _j_t_begin + + _j_m_trap: + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_all_end + mret + + _j_s_trap: + csrrs x25, scause, x0 + csrrs x1, sepc, x0 + addi x1, x1, 4 + csrrw x0, sepc, x1 + sret + + _j_t_begin: + + li x1, 0b110000000000 + csrrc x28, mstatus, x1 + li x1, 0b0000000000000 + csrrs x28, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in u mode... + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend0: + + sd x25, 0(x6) + + li x25, 0x7BAD + + ebreak + + + _jend1: + + sd x25, 8(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend2: + + sd x25, 16(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend3: + + sd x25, 24(x6) + + li x25, 0x7BAD + + ecall + + + _jend4: + + sd x25, 32(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend5: + + sd x25, 40(x6) + + li x25, 0x7BAD + + ebreak + + + _jend6: + + sd x25, 48(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend7: + + sd x25, 56(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend8: + + sd x25, 64(x6) + + li x25, 0x7BAD + + ecall + + + _jend9: + + sd x25, 72(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend10: + + sd x25, 80(x6) + + li x25, 0x7BAD + + ebreak + + + _jend11: + + sd x25, 88(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend12: + + sd x25, 96(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend13: + + sd x25, 104(x6) + + li x25, 0x7BAD + + ecall + + + _jend14: + + sd x25, 112(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend15: + + sd x25, 120(x6) + + li x25, 0x7BAD + + ebreak + + + _jend16: + + sd x25, 128(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend17: + + sd x25, 136(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend18: + + sd x25, 144(x6) + + li x25, 0x7BAD + + ecall + + + _jend19: + + sd x25, 152(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend20: + + sd x25, 160(x6) + + li x25, 0x7BAD + + ebreak + + + _jend21: + + sd x25, 168(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend22: + + sd x25, 176(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend23: + + sd x25, 184(x6) + + li x25, 0x7BAD + + ecall + + + _jend24: + + sd x25, 192(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend25: + + sd x25, 200(x6) + + li x25, 0x7BAD + + ebreak + + + _jend26: + + sd x25, 208(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend27: + + sd x25, 216(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend28: + + sd x25, 224(x6) + + li x25, 0x7BAD + + ecall + + + _jend29: + + sd x25, 232(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend30: + + sd x25, 240(x6) + + li x25, 0x7BAD + + ebreak + + + _jend31: + + sd x25, 248(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend32: + + sd x25, 256(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend33: + + sd x25, 264(x6) + + li x25, 0x7BAD + + ecall + + + _jend34: + + sd x25, 272(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend35: + + sd x25, 280(x6) + + li x25, 0x7BAD + + ebreak + + + _jend36: + + sd x25, 288(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend37: + + sd x25, 296(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend38: + + sd x25, 304(x6) + + li x25, 0x7BAD + + ecall + + + _jend39: + + sd x25, 312(x6) + + li x30, 1 + ecall + _j_all_end: + + csrw mtvec, x31 + # --------------------------------------------------------------------------------------------- + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 40, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END