From d7f0abca5a3cfa087ff544e73de621dd5cbffe59 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 13:17:49 -0700 Subject: [PATCH] Add3d wally32i test --- tests/testgen/PIPELINE.py | 8 +- .../riscv-test-suite/rv32i_m/I/Makefrag | 2 +- .../rv32i_m/I/src/WALLY-PIPELINE.S | 89 ------------------- .../regression/regression-wally.py | 2 +- wally-pipelined/testbench/tests.vh | 4 +- 5 files changed, 8 insertions(+), 97 deletions(-) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S diff --git a/tests/testgen/PIPELINE.py b/tests/testgen/PIPELINE.py index e6b8bde2..6432bb02 100755 --- a/tests/testgen/PIPELINE.py +++ b/tests/testgen/PIPELINE.py @@ -88,10 +88,10 @@ def writeVector(a, b, storecmd, xlen): ################################## # change these to suite your tests -instrs = ["ADD", "SUB", "SLT", "SLTU", "XOR", "OR", "AND"] +instrs = ["ADD"] # "SUB", "XOR", "OR", "AND", "SLT", "SLTU", ] author = "David_Harris@hmc.edu" xlens = [32, 64] -numrand = 100 +numrand = 1000 # setup seed(0) # make tests reproducible @@ -127,10 +127,10 @@ for xlen in xlens: f.write(line) maxreg = 5 - for i in range(1): + for i in range(numrand): instr = instrs[randint(0,len(instrs)-1)] reg1 = randint(0,maxreg) - reg2 = randint(0,maxreg) + reg2 = randint(1,maxreg) reg3 = randint(1,maxreg) line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" f.write(line) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag index e2cdf44d..49f87b20 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag @@ -28,7 +28,7 @@ # Description: Makefrag for RV32I architectural tests rv32i_sc_tests = \ - WALLY-PIPELINE \ + PIPELINE \ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S deleted file mode 100644 index 1fd7866e..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +++ /dev/null @@ -1,89 +0,0 @@ -/////////////////////////////////////////// -// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu -// Created 2021-11-01 11:43:39.219968// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) - -RVTEST_SIGBASE( x8,signature_x8_1) -AND x1, x3, x3 -sw x1, 0(x8) -sw x2, 4(x8) -sw x3, 8(x8) -sw x4, 12(x8) -sw x5, 16(x8) -#endif -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN - - -signature_x8_0: - .fill 0*(XLEN/32),4,0xdeadbeef - - -signature_x8_1: - .fill 19*(XLEN/32),4,0xdeadbeef - - -signature_x1_0: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_1: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_2: - .fill 148*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -RVMODEL_DATA_END -// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 49ca8712..ada9fe38 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -49,7 +49,7 @@ for test in tests64: grepstr="All tests ran without failures") configs.append(tc) #tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] -tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] +tests32 = ["wally32i", "arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] for test in tests32: tc = TestCase( name=test, diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index e897819f..7e33ef68 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -1072,7 +1072,7 @@ string imperas32f[] = '{ string wally64i[] = '{ `WALLYTEST, "rv64i_m/I/add-01", "9010", - "rv64i_m/I/PIPELINE", "2010" + "rv64i_m/I/PIPELINE", "3010" }; string wally64priv[] = '{ @@ -1085,7 +1085,7 @@ string imperas32f[] = '{ string wally32i[] = '{ `WALLYTEST, - "rv64i_m/I/pipeline-01", "9010" + "rv32i_m/I/PIPELINE", "3010" }; string wally32priv[] = '{