From 309a56b8f85c46eb802d74b47c8b19f8f592c9b8 Mon Sep 17 00:00:00 2001 From: Liam Date: Tue, 25 Apr 2023 15:37:04 -0700 Subject: [PATCH 1/4] pmpaddr0 and pmpaddr2 test cases Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2. Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%. --- tests/coverage/pmpcfg.S | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/tests/coverage/pmpcfg.S b/tests/coverage/pmpcfg.S index fd838041..bcc8f395 100644 --- a/tests/coverage/pmpcfg.S +++ b/tests/coverage/pmpcfg.S @@ -1,6 +1,6 @@ // pmpcfg part 1 // Kevin Wan, kewan@hmc.edu, 4/18/2023 -// Liam Chalk, lchalk@hmc.edu, 4/21/2023 +// Liam Chalk, lchalk@hmc.edu, 4/25/2023 // locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. // See the next part in pmpcfg1.S @@ -52,6 +52,26 @@ main: li t0, 0x00001700 csrw pmpcfg3, t0 + li t0, 0x90000000 + csrw pmpaddr0, t0 + li t0, 0x00170000 + csrw pmpcfg0, t0 + + li t0, 0x90000000 + csrw pmpaddr2, t0 + li t0, 0x00170000 + csrw pmpcfg2, t0 + + li t0, 0x90000000 + csrw pmpaddr0, t0 + li t0, 0x17000000 + csrw pmpcfg0, t0 + + li t0, 0x90000000 + csrw pmpaddr2, t0 + li t0, 0x17000000 + csrw pmpcfg2, t0 + li t0, 0x8800000000000000 csrw pmpcfg2, t0 li t0, 0x88000000000000 From 9f417ee93dfdc27ce17864c3efbf7a07fbfa7918 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 25 Apr 2023 17:00:13 -0700 Subject: [PATCH 2/4] extend invalidatecache d$ exclusion to statement coverage --- sim/coverage-exclusions-rv64gc.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index b4441e5b..3db7d049 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -88,7 +88,7 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4 set numcacheways 4 for {set i 0} {$i < $numcacheways} {incr i} { - coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item be 1 -fecexprrow 4 + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4 } # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY From 2f49ee18feb380dc25fdac4c61fd5a74e6b7d8d9 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 25 Apr 2023 17:02:53 -0700 Subject: [PATCH 3/4] Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign FlushWay is always 1 for one way, but by default it is only 1 for way 0. The logic that advances FlushWay to ways 1, 2, and 3 only does so on a subset of conditions that SelFlush is high (in cachefsm), so this is unreachable for cachways 1-3. --- src/cache/cacheway.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 368c7b58..095b8c1d 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -82,6 +82,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected. + // coverage off -item e 1 -fecexprrow 3 + // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases. assign FlushWayEn = FlushWay & SelFlush; assign SelNonHit = FlushWayEn | SetValid | SelWriteback; end From 6299c0ef0ba3fc1cbbef840c29f90bd814865803 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 25 Apr 2023 20:30:46 -0700 Subject: [PATCH 4/4] Cacheway Exclude FlushStage=1 when SetValidWay=1 We determined that this case is not hit even for i$, so this case is also excluded separately for i$. It could be a better idea to remove the ~FlushStage check completely (if we're sure). My reasoning for this one is written as a comment in the exclusion script: since a pipeline stall is asserted by the cache in the fetch stage (which happens before going into the WRITE_LINE state and asserting SetValidWay), there seems to be no way to trigger a FlushStage (FlushW for D$) while the stallM is active. --- sim/coverage-exclusions-rv64gc.do | 6 +++++- src/cache/cacheway.sv | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 3db7d049..241c9b06 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -77,7 +77,7 @@ for {set i 0} {$i < $numcacheways} {incr i} { coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1 coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6 # below: flushD can't go high during an icache write b/c of pipeline stall - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 } ## D$ Exclusions. @@ -89,6 +89,10 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get set numcacheways 4 for {set i 0} {$i < $numcacheways} {incr i} { coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4 + + # FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before + # going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW. + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 } # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 095b8c1d..f504f40a 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -102,7 +102,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay assign ClearDirtyWay = ClearDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn - assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: icache SetValidEN + assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN // If writing the whole line set all write enables to 1, else only set the correct word. assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR