diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index 823620b7..4c602659 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -28,39 +28,45 @@ `include "wally-config.vh" module dmem ( - input logic clk, reset, - input logic FlushW, - // - input logic [1:0] MemRWM, - output logic [1:0] MemRWdcuoutM, - output logic DataMisalignedM, - - input logic [`XLEN-1:0] DataAdrM, + input logic clk, reset, + input logic FlushW, + output logic DataStall, + // Memory Stage + input logic [1:0] MemRWM, + input logic [`XLEN-1:0] MemAdrM, input logic [2:0] Funct3M, input logic [`XLEN-1:0] ReadDataM, + input logic [`XLEN-1:0] WriteDataM, + output logic [`XLEN-1:0] MemPAdrM, + output logic [1:0] MemRWAlignedM, + output logic DataMisalignedM, + // Writeback Stage + input logic MemAckW, output logic [`XLEN-1:0] ReadDataW, -/* input logic [`XLEN-1:0] WriteDataM, */ // faults - input logic DataAccessFaultM, - output logic LoadMisalignedFaultM, LoadAccessFaultM, - output logic StoreMisalignedFaultM, StoreAccessFaultM + input logic DataAccessFaultM, + output logic LoadMisalignedFaultM, LoadAccessFaultM, + output logic StoreMisalignedFaultM, StoreAccessFaultM ); - // Pipeline register + // Initially no MMU + assign MemPAdrM = MemAdrM; + + // Pipeline register *** AHB data will eventually come back in W anyway floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataM, ReadDataW); // Determine if an Unaligned access is taking place always_comb case(Funct3M[1:0]) 2'b00: DataMisalignedM = 0; // lb, sb, lbu - 2'b01: DataMisalignedM = DataAdrM[0]; // lh, sh, lhu - 2'b10: DataMisalignedM = DataAdrM[1] | DataAdrM[0]; // lw, sw, flw, fsw, lwu - 2'b11: DataMisalignedM = |DataAdrM[2:0]; // ld, sd, fld, fsd + 2'b01: DataMisalignedM = MemAdrM[0]; // lh, sh, lhu + 2'b10: DataMisalignedM = MemAdrM[1] | MemAdrM[0]; // lw, sw, flw, fsw, lwu + 2'b11: DataMisalignedM = |MemAdrM[2:0]; // ld, sd, fld, fsd endcase // Squash unaligned data accesses // *** this is also the place to squash if the cache is hit - assign MemRWdcuoutM = MemRWM & {2{~DataMisalignedM}}; + assign MemRWAlignedM = MemRWM & {2{~DataMisalignedM}}; // Determine if address is valid assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; @@ -68,6 +74,8 @@ module dmem ( assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; assign StoreAccessFaultM = DataAccessFaultM & MemRWM[0]; + // Data stall + assign DataStall = 0; endmodule diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index bbbbe454..8ce17545 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -35,14 +35,14 @@ module ahblite ( // Load control input logic UnsignedLoadM, // Signals from Instruction Cache - input logic [`XLEN-1:0] IPAdrF, + input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram input logic IReadF, output logic [`XLEN-1:0] IRData, // output logic IReady, // Signals from Data Cache - input logic [`XLEN-1:0] DPAdrM, + input logic [`XLEN-1:0] MemPAdrM, input logic DReadM, DWriteM, - input logic [`XLEN-1:0] DWDataM, + input logic [`XLEN-1:0] WriteDataM, input logic [1:0] DSizeM, // Return from bus output logic [`XLEN-1:0] DRData, @@ -59,8 +59,10 @@ module ahblite ( output logic [3:0] HPROT, output logic [1:0] HTRANS, output logic HMASTLOCK, + // Acknowledge + output logic InstrAckD, MemAckW // Stalls - output logic InstrStall, DataStall +// output logic InstrStall, DataStall ); logic GrantData; @@ -83,8 +85,8 @@ module ahblite ( endgenerate // drive bus outputs - assign HADDR = GrantData ? DPAdrM[31:0] : IPAdrF[31:0]; - assign HWDATA = DWDataM; + assign HADDR = GrantData ? MemPAdrM[31:0] : InstrPAdrF[31:0]; + assign HWDATA = WriteDataM; //flop #(`XLEN) wdreg(HCLK, DWDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN assign HWRITE = DWriteM; assign HSIZE = GrantData ? {1'b0, DSizeM} : ISize; @@ -102,9 +104,9 @@ module ahblite ( // stalls // Stall MEM stage if data is being accessed and bus isn't yet ready - assign DataStall = GrantData & ~HREADY; + //assign DataStall = GrantData & ~HREADY; // Stall Fetch stage if instruction should be read but reading data or bus isn't ready - assign InstrStall = IReadF & (GrantData | ~HREADY); + //assign InstrStall = IReadF & (GrantData | ~HREADY); // *** consider adding memory access faults based on HRESP being high // InstrAccessFaultF, DataAccessFaultM, diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index 3256634b..30603637 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -48,7 +48,7 @@ module datapath ( input logic [`XLEN-1:0] ReadDataW, input logic RetM, TrapM, output logic [`XLEN-1:0] SrcAM, - output logic [`XLEN-1:0] WriteDataM, DataAdrM, + output logic [`XLEN-1:0] WriteDataM, MemAdrM, // Writeback stage signals input logic FlushW, input logic RegWriteW, @@ -103,7 +103,7 @@ module datapath ( // Memory stage pipeline register floprc #(`XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM); floprc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM); - assign DataAdrM = ALUResultM; + assign MemAdrM = ALUResultM; floprc #(`XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataM); floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM); diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 48f9a9df..7ed4bdff 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -38,7 +38,7 @@ module ieu ( input logic DataMisalignedM, input logic DataAccessFaultM, output logic [1:0] MemRWM, - output logic [`XLEN-1:0] DataAdrM, WriteDataM, + output logic [`XLEN-1:0] MemAdrM, WriteDataM, output logic [`XLEN-1:0] SrcAM, output logic [2:0] Funct3M, // Writeback stage diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 360023ad..3a12b330 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -32,6 +32,9 @@ module ifu ( // Fetch input logic [31:0] InstrF, output logic [`XLEN-1:0] PCF, + output logic [`XLEN-1:0] InstrPAdrF, + // Decode + output logic InstrStall, // Execute input logic PCSrcE, input logic [`XLEN-1:0] PCTargetE, @@ -60,6 +63,8 @@ module ifu ( logic [31:0] nop = 32'h00000013; // instruction for NOP // *** put memory interface on here, InstrF becomes output + assign InstrStall = 0; // *** + assign InstrPAdrF = PCF; // *** no MMU assign PrivilegedChangePCM = RetM | TrapM; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index a4bb19b6..be97b51c 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -42,7 +42,7 @@ module privileged ( input logic LoadMisalignedFaultM, LoadAccessFaultM, input logic StoreMisalignedFaultM, StoreAccessFaultM, input logic TimerIntM, ExtIntM, SwIntM, - input logic [`XLEN-1:0] InstrMisalignedAdrM, DataAdrM, + input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, input logic FlushD, FlushE, FlushM, StallD diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 349e8c91..8120ab95 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -37,7 +37,7 @@ module trap ( input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, input logic [11:0] MIP_REGW, MIE_REGW, input logic STATUS_MIE, STATUS_SIE, - input logic [`XLEN-1:0] InstrMisalignedAdrM, DataAdrM, + input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [31:0] InstrM, output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM @@ -107,11 +107,11 @@ module trap ( always_comb if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM; - else if (LoadMisalignedFaultM) NextFaultMtvalM = DataAdrM; - else if (StoreMisalignedFaultM) NextFaultMtvalM = DataAdrM; + else if (LoadMisalignedFaultM) NextFaultMtvalM = MemAdrM; + else if (StoreMisalignedFaultM) NextFaultMtvalM = MemAdrM; else if (InstrPageFaultM) NextFaultMtvalM = 0; // *** implement - else if (LoadPageFaultM) NextFaultMtvalM = DataAdrM; - else if (StorePageFaultM) NextFaultMtvalM = DataAdrM; + else if (LoadPageFaultM) NextFaultMtvalM = MemAdrM; + else if (StorePageFaultM) NextFaultMtvalM = MemAdrM; else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; else NextFaultMtvalM = 0; endmodule \ No newline at end of file diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index dcf1490f..408045e2 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -79,11 +79,13 @@ module wallypipelinedhart ( logic FloatRegWriteW; // bus interface to dmem - logic [1:0] MemRWdcuoutM; + logic [1:0] MemRWAlignedM; logic [2:0] Funct3M; - logic [`XLEN-1:0] DataAdrM, WriteDataM; + logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM; logic [`XLEN-1:0] ReadDataM, ReadDataW; + logic [`XLEN-1:0] InstrPAdrF; logic DataStall, InstrStall; + logic InstrAckD, MemAckW; ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache @@ -91,8 +93,8 @@ module wallypipelinedhart ( dmem dmem(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit ahblite ebu( // *** make IRData InstrF - .IPAdrF(PCF), .IReadF(1'b1), .IRData(), //.IReady(), - .DPAdrM(DataAdrM), .DReadM(MemRWdcuoutM[1]), .DWriteM(MemRWdcuoutM[0]), .DWDataM(WriteDataM), + .IReadF(1'b1), .IRData(), //.IReady(), + .DReadM(MemRWAlignedM[1]), .DWriteM(MemRWAlignedM[0]), .DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(), .UnsignedLoadM(Funct3M[2]), .*);