diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv
index 6f9c0855..6d620047 100644
--- a/wally-pipelined/src/cache/cacheway.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -31,7 +31,6 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
    input logic 			      reset,
 
    input logic [$clog2(NUMLINES)-1:0] RAdr,
-   input logic [$clog2(NUMLINES)-1:0] WAdr, 
    input logic [`PA_BITS-1:0] 	      PAdr,
    input logic 			      WriteEnable,
    input logic 			      VDWriteEnable, 
@@ -64,7 +63,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   logic [TAGLEN-1:0] 		      VicDirtyWay;
   logic [TAGLEN-1:0] 		      FlushThisWay;
 
-  logic [$clog2(NUMLINES)-1:0] 	      RAdrD, WAdrD;
+  logic [$clog2(NUMLINES)-1:0] 	      RAdrD;
   logic 			      SetValidD, ClearValidD;
   logic 			      SetDirtyD, ClearDirtyD;
   logic 			      WriteEnableD, VDWriteEnableD;
@@ -76,23 +75,20 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 
   generate
     for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word
-      sram1rw #(.DEPTH(`XLEN), 
-		.WIDTH(NUMLINES))
-      CacheDataMem(.clk(clk),
-		   .Addr(RAdr),
-		   .ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ),
-		   .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
-		   .WriteEnable(WriteEnable & WriteWordEnable[words]));
+      sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES))
+      CacheDataMem(.clk(clk), .Addr(RAdr),
+				   .ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ),
+				   .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
+				   .WriteEnable(WriteEnable & WriteWordEnable[words]));
     end
   endgenerate
 
-  sram1rw #(.DEPTH(TAGLEN),
-	    .WIDTH(NUMLINES))
+  sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
   CacheTagMem(.clk(clk),
-	      .Addr(RAdr),
-	      .ReadData(ReadTag),
-	      .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
-	      .WriteEnable(TagWriteEnable));
+			  .Addr(RAdr),
+			  .ReadData(ReadTag),
+			  .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
+			  .WriteEnable(TagWriteEnable));
 
   assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
   assign SelectedWay = SelFlush ? FlushWay : 
@@ -101,10 +97,6 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 
   assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid :
 			  VictimWay & Dirty & Valid;
-/* -----\/----- EXCLUDED -----\/-----
-  assign VictimTagWay = SelFlush & FlushWay ? ReadTag :
-			VictimWay ? ReadTag : '0;
- -----/\----- EXCLUDED -----/\----- */
 
   assign VicDirtyWay = VictimWay ? ReadTag : '0;
   assign FlushThisWay = FlushWay ? ReadTag : '0;
@@ -116,13 +108,12 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   	ValidBits <= {NUMLINES{1'b0}};
     else if (InvalidateAll) 
   	ValidBits <= {NUMLINES{1'b0}};
-    else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b1;
-    else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b0;
+    else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b1;
+    else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b0;
   end
 
   always_ff @(posedge clk) begin
     RAdrD <= RAdr;
-    WAdrD <= WAdr;
     SetValidD <= SetValid;
     ClearValidD <= ClearValid;    
     WriteEnableD <= WriteEnable;
@@ -137,8 +128,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
       always_ff @(posedge clk) begin
 	if (reset) 
   	  DirtyBits <= {NUMLINES{1'b0}};
-	else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1;
-	else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0;
+	else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1;
+	else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0;
       end
 
       always_ff @(posedge clk) begin
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 827dcb1b..bf8980da 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -126,29 +126,19 @@ module dcache
 			.s(SelAdrM),
 			.y(RAdr));
 
-  cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
-  MemWay[NUMWAYS-1:0](.clk,
-					  .reset,
-					  .RAdr,
-					  .WAdr(RAdr),  // *** Reduce after addressing in icache also
+  cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), 
+			 .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
+  MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
 					  .PAdr(LsuPAdrM),
 					  .WriteEnable(SRAMWayWriteEnable),
 					  .VDWriteEnable(VDWriteEnableWay),
 					  .WriteWordEnable(SRAMWordEnable),
 					  .TagWriteEnable(SRAMBlockWayWriteEnableM), 
 					  .WriteData(SRAMWriteData),
-					  .SetValid,
-					  .ClearValid,
-					  .SetDirty,
-					  .ClearDirty,
-					  .SelEvict,
-					  .VictimWay,
-					  .FlushWay,
-					  .SelFlush,
+					  .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
+					  .VictimWay, .FlushWay, .SelFlush,
 					  .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM),
-					  .WayHit,
-					  .VictimDirtyWay,
-					  .VictimTagWay,
+					  .WayHit, .VictimDirtyWay, .VictimTagWay,
 					  .InvalidateAll(1'b0));
 
   generate
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 4b300007..874ed7f1 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -132,12 +132,9 @@ module icache
 
   
 
-  cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN),
-	     .DIRTY_BITS(0))
-  MemWay[NUMWAYS-1:0](.clk,
-		      .reset,
-		      .RAdr(RAdr),
-		      .WAdr(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),		      
+  cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), 
+			 .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
+  MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
 		      .PAdr(PCTagF),
 		      .WriteEnable(SRAMWayWriteEnable),
 		      .VDWriteEnable(1'b0),
@@ -145,19 +142,12 @@ module icache
 		      .TagWriteEnable(SRAMWayWriteEnable),
 		      .WriteData(ICacheMemWriteData),
 		      .SetValid(ICacheMemWriteEnable),
-		      .ClearValid(1'b0),
-		      .SetDirty(1'b0),
-		      .ClearDirty(1'b0),
-		      .SelEvict(1'b0),
+		      .ClearValid(1'b0), .SetDirty(1'b0), .ClearDirty(1'b0), .SelEvict(1'b0),
 		      .VictimWay,
-		      .FlushWay(1'b0),
-		      .SelFlush(1'b0),
-		      .ReadDataBlockWayMasked,
-		      .WayHit,
-		      .VictimDirtyWay(),
-		      .VictimTagWay(),
-		      .InvalidateAll(InvalidateICacheM)
-		      );
+		      .FlushWay(1'b0), .SelFlush(1'b0),
+		      .ReadDataBlockWayMasked, .WayHit,
+		      .VictimDirtyWay(), .VictimTagWay(),
+		      .InvalidateAll(InvalidateICacheM));
   
   generate
     if(NUMWAYS > 1) begin