From d3e39763b60efc300fa5bf815c1bde5b7152dea0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 2 Aug 2022 07:34:09 -0700 Subject: [PATCH] Moved InvA to sign block; simplified fmaexpadd coding --- pipelined/src/fpu/fma.sv | 2 +- pipelined/src/fpu/fmaadd.sv | 7 +------ pipelined/src/fpu/fmaexpadd.sv | 7 +++++-- pipelined/src/fpu/fmasign.sv | 8 +++++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index de1fdabf..d12f497e 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -72,7 +72,7 @@ module fma( // Alignment shifter /////////////////////////////////////////////////////////////////////////////// // calculate the signs and take the opperation into account - fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As); + fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA); fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye, .Am, .ZmSticky, .KillProd); diff --git a/pipelined/src/fpu/fmaadd.sv b/pipelined/src/fpu/fmaadd.sv index 53ed023f..653b9b3e 100644 --- a/pipelined/src/fpu/fmaadd.sv +++ b/pipelined/src/fpu/fmaadd.sv @@ -33,6 +33,7 @@ module fmaadd( input logic [3*`NF+5:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1) input logic [2*`NF+1:0] Pm, // the product's mantissa input logic Ps, As,// the product sign and the alligend addeded's sign (Modified Z sign for other opperations) + input logic InvA, // invert the aligned addend input logic KillProd, // should the product be set to 0 input logic ZmSticky, input logic [`NE-1:0] Ze, @@ -40,7 +41,6 @@ module fmaadd( output logic [3*`NF+5:0] AmInv, // aligned addend possibly inverted output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed output logic NegSum, // was the sum negitive - output logic InvA, // do you invert the aligned addend output logic Ss, output logic [`NE+1:0] Se, output logic [3*`NF+5:0] Sm // the positive sum @@ -51,11 +51,6 @@ module fmaadd( // Addition /////////////////////////////////////////////////////////////////////////////// - // Negate Z when doing one of the following opperations: - // -prod + Z - // prod - Z - assign InvA = As ^ Ps; - // Choose an inverted or non-inverted addend - the one has to be added now for the LZA assign AmInv = InvA ? ~Am : Am; // Kill the product if the product is too small to effect the addition (determined in fma1.sv) diff --git a/pipelined/src/fpu/fmaexpadd.sv b/pipelined/src/fpu/fmaexpadd.sv index 1d208327..d39dfadd 100644 --- a/pipelined/src/fpu/fmaexpadd.sv +++ b/pipelined/src/fpu/fmaexpadd.sv @@ -36,7 +36,10 @@ module fmaexpadd( output logic [`NE+1:0] Pe // product's exponent B^(1023)NE+2 ); + logic PZero; + // kill the exponent if the product is zero - either X or Y is 0 - assign Pe = ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)})&{`NE+2{~(XZero|YZero)}}; + assign PZero = XZero | YZero; + assign Pe = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)}); -endmodule \ No newline at end of file +endmodule diff --git a/pipelined/src/fpu/fmasign.sv b/pipelined/src/fpu/fmasign.sv index 66c1af83..936eea21 100644 --- a/pipelined/src/fpu/fmasign.sv +++ b/pipelined/src/fpu/fmasign.sv @@ -33,7 +33,8 @@ module fmasign( input logic [2:0] OpCtrl, // opperation contol input logic Xs, Ys, Zs, // sign of the inputs output logic Ps, // the product's sign - takes opperation into account - output logic As // aligned addend sign used in fma - takes opperation into account + output logic As, // aligned addend sign used in fma - takes opperation into account + output logic InvA // Effective subtraction: invert addend ); // Calculate the product's sign @@ -41,7 +42,8 @@ module fmasign( // flip is negation opperation assign Ps = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]); - // flip if subtraction + // flip addend sign for subtraction assign As = Zs^OpCtrl[0]; - + // Effective subtraction when product and addend have opposite signs + assign InvA = As ^ Ps; endmodule