From 0c88ddeb5ae933d639b5a4fa15c9c3877c923932 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 10:44:37 -0600 Subject: [PATCH 1/2] Simplified the dcache to bus address generation. --- wally-pipelined/regression/wave.do | 9 +++++---- wally-pipelined/src/cache/dcache.sv | 6 +++--- wally-pipelined/src/lsu/lsu.sv | 29 ++++++++++++++++------------- 3 files changed, 24 insertions(+), 20 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 29ca4b71..e53e1a87 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -232,7 +232,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable} @@ -337,7 +336,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group status /testb add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCFetchLine add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCWriteLine -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BUSACK add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay @@ -469,8 +467,11 @@ add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate /testbench/dut/hart/priv/priv/csr/MEPC_REGW +add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr +add wave -noupdate /testbench/dut/hart/lsu/BasePAdrMaskedM +add wave -noupdate /testbench/dut/hart/lsu/match TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {47921 ns} 0} {{Cursor 4} {49574 ns} 1} +WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {35021 ns} 0} {{Cursor 4} {49574 ns} 1} quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -486,4 +487,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {47459 ns} {48279 ns} +WaveRestoreZoom {34887 ns} {35269 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index efcd8056..ccfc7fa3 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -50,7 +50,7 @@ module dcache input logic BUSACK, - output logic [`PA_BITS-1:0] BasePAdrM, + output logic [`PA_BITS-1:0] DCacheBusAdr, output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], output logic SelFlush, @@ -232,11 +232,11 @@ module dcache .y(SRAMWriteData)); - mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), + mux3 #(`PA_BITS) BaseAdrMux(.d0({MemPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), .s({SelFlush, SelEvict}), - .y(BasePAdrM)); + .y(DCacheBusAdr)); // flush address and way generation. diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index cfec7203..d325f1ad 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -99,7 +99,7 @@ module lsu logic [1:0] LsuRWM; logic [2:0] LsuFunct3M; logic [1:0] LsuAtomicM; - logic [`PA_BITS-1:0] LsuPAdrM; + logic [`PA_BITS-1:0] LsuPAdrM, LocalLsuBusAdr; logic [11:0] LsuAdrE, DCAdrE; logic CPUBusy; logic MemReadM; @@ -332,7 +332,6 @@ module lsu localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); // temp - logic SelUncached; logic WordCountFlag; logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; @@ -351,7 +350,7 @@ module lsu logic CntEn, PreCntEn; logic CntReset; - logic [`PA_BITS-1:0] BasePAdrM; + logic [`PA_BITS-1:0] DCacheBusAdr; logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0]; @@ -362,7 +361,8 @@ module lsu logic UnCachedLsuBusRead; logic UnCachedLsuBusWrite; - + logic SelUncachedAdr; + dcache dcache(.clk, .reset, .CPUBusy, .MemRWM(DCRWM), @@ -375,7 +375,7 @@ module lsu .DCacheMiss, .DCacheAccess, .IgnoreRequest, .CacheableM(CacheableM), .DCCommittedM, - .BasePAdrM, + .DCacheBusAdr, .ReadDataBlockSetsM, .SelFlush, .DCacheMemWriteData, @@ -387,7 +387,7 @@ module lsu mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[`XLEN-1:0]), - .s(SelUncached), + .s(SelUncachedAdr), .y(ReadDataWordMuxM)); // finally swr @@ -435,12 +435,11 @@ module lsu endgenerate - // if not cacheable the offset bits needs to be sent to the EBU. - // if cacheable the offset bits are discarded. $ FSM will fetch the whole block. - assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; - assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; - - assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM; + + //assign LocalLsuBusAdr = SelUncachedAdr ? MemPAdrM : {DCacheBusAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}} ; + assign LocalLsuBusAdr = SelUncachedAdr ? MemPAdrM : DCacheBusAdr ; + + assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr; assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[WordCount]; @@ -504,7 +503,6 @@ module lsu (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign SelUncached = BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_CPU_BUSY; assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCRWM[0])) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); @@ -517,6 +515,11 @@ module lsu assign BUSACK = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCRWM & ~CacheableM)) | + (BusCurrState == STATE_BUS_UNCACHED_READ | + BusCurrState == STATE_BUS_UNCACHED_READ_DONE | + BusCurrState == STATE_BUS_UNCACHED_WRITE | + BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE); endmodule From 81b382e51eeb600ab276a3a98aac6bdb9a091cfc Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 29 Dec 2021 18:52:52 +0000 Subject: [PATCH 2/2] Switched riscv-arch-test to current hash --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99b..307c77b2 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86