diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc
index 339951e5..e1a23c1e 100644
--- a/fpga/constraints/constraints-ArtyA7.xdc
+++ b/fpga/constraints/constraints-ArtyA7.xdc
@@ -5,7 +5,7 @@
 
 # clock comes from pin E3 and is 100Mhz
 # output of mmcm is /4 => 25Mhz
-create_clock -period 25.000 -name mmcm_clkout1 -waveform {0.000 12.500} [get_nets xlnx_ddr3_c0/ui_clk]
+#create_clock -period 25.000 -name mmcm_clkout1 -waveform {0.000 12.500} [get_nets xlnx_ddr3_c0/ui_clk]
 
 create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
 
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 642074a8..a2a2b8c6 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -18,6 +18,7 @@ read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/x
 
 if {$board=="ArtyA7"} {
     read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci
+    read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci
 } else {
     read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
 }
diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v
index da7ad450..8de9c66b 100644
--- a/fpga/src/fpgaTopArtyA7.v
+++ b/fpga/src/fpgaTopArtyA7.v
@@ -173,6 +173,8 @@ module fpgaTop
   wire             ui_clk_sync_rst;
   
   wire 			   CLK208;
+  wire             clk167;
+  wire             clk200;
 
   wire             app_sr_active;
   wire             app_ref_ack;
@@ -185,6 +187,20 @@ module fpgaTop
   assign ahblite_resetn = peripheral_aresetn;
   assign cpu_reset = bus_struct_reset;
   assign calib = c0_init_calib_complete;
+
+  // mmcm
+
+  // the ddr3 mig7 requires 2 input clocks 
+  // 1. sys clock which is 167 MHz = ddr3 clock / 4
+  // 2. a second clock which is 200 MHz
+  // Wally requires a slower clock.  At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz.
+  // the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot.
+  xlnx_mmcm xln_mmcm(.clk_out1(clk167),
+                     .clk_out2(clk200),
+                     .clk_out3(CPUCLK),
+                     .reset(reset),
+                     .locked(),
+                     .clk_in1(default_100mhz_clk));
   
   // SD Card Tristate
   IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low
@@ -398,10 +414,10 @@ module fpgaTop
      .ddr3_odt(ddr3_odt),
 
      // clocks. I still don't understand why this needs two?
-     .sys_clk_i(default_100mhz_clk),
-     .clk_ref_i(default_100mhz_clk),
+     .sys_clk_i(clk167),
+     .clk_ref_i(clk200),
 
-     .ui_clk(CLK208),
+     .ui_clk(BUSCLK),
      .ui_clk_sync_rst(ui_clk_sync_rst),
      .aresetn(~reset),
      .sys_rst(reset),