diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv
index b2810183..01a378f2 100644
--- a/wally-pipelined/src/privileged/csrs.sv
+++ b/wally-pipelined/src/privileged/csrs.sv
@@ -89,8 +89,7 @@ module csrs #(parameter
       flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
       flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); 
       flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW);
-      if(`QEMU) assign STVAL_REGW = `XLEN'b0;
-      else flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
+      flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
       if (`MEM_VIRTMEM)
         flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
       else
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index 3db2f8cb..6f4596ba 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -175,12 +175,12 @@ module testbench();
   `define MEPC        `CSR_BASE.csrm.MEPCreg.q
   `define SEPC        `CSR_BASE.csrs.genblk1.SEPCreg.q
   `define MCOUNTEREN  `CSR_BASE.csrm.genblk3.MCOUNTERENreg.q
-  `define SCOUNTEREN  `CSR_BASE.csrs.genblk1.genblk3.SCOUNTERENreg.q
+  `define SCOUNTEREN  `CSR_BASE.csrs.genblk1.genblk2.SCOUNTERENreg.q
   `define MSCRATCH    `CSR_BASE.csrm.MSCRATCHreg.q
   `define SSCRATCH    `CSR_BASE.csrs.genblk1.SSCRATCHreg.q
   `define MTVEC       `CSR_BASE.csrm.MTVECreg.q
   `define STVEC       `CSR_BASE.csrs.genblk1.STVECreg.q
-  `define SATP        `CSR_BASE.csrs.genblk1.genblk2.SATPreg.q
+  `define SATP        `CSR_BASE.csrs.genblk1.genblk1.SATPreg.q
   `define MSTATUS     `CSR_BASE.csrsr.MSTATUS_REGW
   `define STATUS_TSR  `CSR_BASE.csrsr.STATUS_TSR_INT
   `define STATUS_TW   `CSR_BASE.csrsr.STATUS_TW_INT