diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
index 5e1f2725..b0beae6d 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -92,7 +92,7 @@ module fdivsqrtiter(
   logic [1:0] initCSqrt, initCDiv2, initCDiv4, initCUpper;
   assign initCSqrt = 2'b11;
   assign initCDiv2 = 2'b10;
-  assign initCDiv4 = 2'b10; // *** not sure why this works; seems like it should be 00 for initializing to -4
+  assign initCDiv4 = 2'b00; // *** not sure why this works; seems like it should be 00 for initializing to -4
   assign initCUpper = SqrtE ? initCSqrt : (`RADIX == 4) ? initCDiv4 : initCDiv2;
   assign initC = {initCUpper, {`DIVb{1'b0}}};
 
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv
index 8e36ad88..8b6fc093 100644
--- a/pipelined/src/fpu/postproc/divshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/divshiftcalc.sv
@@ -42,11 +42,8 @@ module divshiftcalc(
 );
     logic [`LOGNORMSHIFTSZ-1:0] NormShift, DivDenormShiftAmt;
     logic [`NE+1:0] DivDenormShift;
-    logic [`NORMSHIFTSZ-1:0] PreDivShiftIn;
-
-    logic [`DURLEN-1:0] DivEarlyTermShift = 0;
-
-    // is the result denromalized
+ 
+    // is the result denormalized
     // if the exponent is 1 then the result needs to be normalized then the result is denormalizes
     assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
 
@@ -74,8 +71,5 @@ module divshiftcalc(
     assign DivDenormShiftAmt = DivDenormShiftPos ? DivDenormShift[`LOGNORMSHIFTSZ-1:0] : '0;
     assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift;
 
-    // *** explain why radix 4 division needs a left shift by 1
-    // *** can this shift be moved into the shiftcorrection logic?
-    assign PreDivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
-    assign DivShiftIn = PreDivShiftIn << (`RADIX==4 & ~Sqrt); 
+    assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
 endmodule