From cd75bf98e11474972e29949f5f17d74b588bf38e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 8 Jan 2022 20:49:45 -0600 Subject: [PATCH] If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss. This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM. --- pipelined/src/lsu/interlockfsm.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 03cff4b0..2540aaf6 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -64,7 +64,8 @@ module interlockfsm always_comb begin case(InterlockCurrState) - STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; + STATE_T0_READY: if (TrapM) InterlockNextState = STATE_T0_READY; + else if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS; else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS; else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS;