diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 80cd4e3a..044ebdcc 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -64,16 +64,16 @@ module fdivsqrt( logic [`DIVb+1:0] FirstC; logic Firstun; logic WZeroM, AZeroM, BZeroM, AZeroE, BZeroE; - logic SpecialCaseM; + logic SpecialCaseM, MDUM; logic [`DIVBLEN:0] nE, nM, mM; - logic CalcOTFCSwapE, OTFCSwapE, ALTBM, As; + logic CalcOTFCSwapE, OTFCSwapE, ALTBM, AsM; logic DivStartE; logic [`XLEN-1:0] ForwardedSrcAM; fdivsqrtpreproc fdivsqrtpreproc( .clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), - .Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, .ForwardedSrcAM, - .nE, .nM, .mM, .CalcOTFCSwapE, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As, + .Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, .ForwardedSrcAM, .MDUM, + .nE, .nM, .mM, .CalcOTFCSwapE, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .AsM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, .nE, @@ -87,8 +87,8 @@ module fdivsqrt( .IFDivStartE, .CalcOTFCSwapE, .OTFCSwapE, .FDivBusyE); fdivsqrtpostproc fdivsqrtpostproc( - .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, + .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .MDUM, .SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAM, - .nM, .ALTBM, .mM, .BZeroM, .As, .OTFCSwapEM(OTFCSwapE), + .nM, .ALTBM, .mM, .BZeroM, .AsM, .OTFCSwapEM(OTFCSwapE), .QmM, .WZeroM, .DivSM, .FPIntDivResultM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 5f914298..e963df4a 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -37,7 +37,7 @@ module fdivsqrtpostproc( input logic [`DIVb+1:0] FirstC, input logic Firstun, SqrtM, SpecialCaseM, OTFCSwapEM, input logic [`XLEN-1:0] ForwardedSrcAM, - input logic RemOpM, ALTBM, BZeroM, As, + input logic RemOpM, ALTBM, BZeroM, AsM, MDUM, input logic [`DIVBLEN:0] nM, mM, output logic [`DIVb:0] QmM, output logic WZeroM, @@ -45,7 +45,7 @@ module fdivsqrtpostproc( output logic [`XLEN-1:0] FPIntDivResultM ); - logic [`DIVb+3:0] W, Sum, RemDM; + logic [`DIVb+3:0] W, Sum, DM; logic [`DIVb:0] PreQmM; logic NegStickyM, PostIncM; logic weq0; @@ -64,7 +64,7 @@ module fdivsqrtpostproc( logic [`DIVb+3:0] WCF, WSF; assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1)); - assign FZero = SqrtM ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b001,D,1'b0}; + assign FZero = (SqrtM & ~MDUM) ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b001,D,1'b0}; csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero}; aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0); assign WZeroM = weq0|(wfeq0 & Firstun); @@ -77,14 +77,14 @@ module fdivsqrtpostproc( assign Sum = WC + WS; assign W = $signed(Sum) >>> `LOGR; assign NegStickyM = W[`DIVb+3]; - assign RemDM = {4'b0000, D}; + assign DM = {4'b0001, D}; // Integer division: sign handling for div and rem always_comb - if (~As) + if (~AsM) if (NegStickyM) begin NormQuotM = FirstUM; - NormRemM = W + RemDM; + NormRemM = W + DM; PostIncM = 0; end else begin NormQuotM = FirstU; @@ -98,8 +98,8 @@ module fdivsqrtpostproc( PostIncM = 0; end else begin NormQuotM = FirstU; - NormRemM = W - RemDM; - PostIncM = 1; + NormRemM = W - DM; + PostIncM = ~ALTBM; end // Integer division: Special cases diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 902b0276..c68cd25d 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -42,7 +42,8 @@ module fdivsqrtpreproc ( input logic [2:0] Funct3E, input logic MDUE, W64E, output logic [`DIVBLEN:0] nE, nM, mM, - output logic CalcOTFCSwapE, OTFCSwapE, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE, + output logic CalcOTFCSwapE, OTFCSwapE, ALTBM, MDUM, + output logic AsM, AZeroM, BZeroM, AZeroE, BZeroE, output logic [`NE+1:0] QeM, output logic [`DIVb+3:0] X, output logic [`DIVb-1:0] DPreproc, @@ -56,7 +57,7 @@ module fdivsqrtpreproc ( // Intdiv signals logic [`DIVb-1:0] IFNormLenX, IFNormLenD; logic [`XLEN-1:0] PosA, PosB; - logic Bs, ALTBE; + logic AsE, BsE, ALTBE; logic [`XLEN-1:0] A64, B64; logic [`DIVBLEN:0] mE; logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX; @@ -68,15 +69,15 @@ module fdivsqrtpreproc ( // ***can probably merge X LZC with conversion // cout the number of leading zeros - assign As = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0]; - assign Bs = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0]; - assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE; - assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE; + assign AsE = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0]; + assign BsE = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0]; + assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE; + assign B64 = W64E ? {{(`XLEN-32){BsE}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE; - assign CalcOTFCSwapE = (As ^ Bs) & MDUE; + assign CalcOTFCSwapE = (AsE ^ BsE) & MDUE; - assign PosA = As ? -A64 : A64; - assign PosB = Bs ? -B64 : B64; + assign PosA = AsE ? -A64 : A64; + assign PosB = BsE ? -B64 : B64; assign AZeroE = ~(|ForwardedSrcAE); assign BZeroE = ~(|ForwardedSrcBE); @@ -128,6 +129,8 @@ module fdivsqrtpreproc ( flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM); flopen #(1) azeroreg(clk, IFDivStartE, AZeroE, AZeroM); flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM); + flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM); + flopen #(1) mdureg(clk, IFDivStartE, MDUE, MDUM); flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM); flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM); flopen #(`XLEN) srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM);