diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 0be7fcdd..11876dde 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -#do ./wave-dos/linux-waves.do +do ./wave-dos/linux-waves.do #-- Run the Simulation diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index d8383965..d73a85bc 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -33,15 +33,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // Input the address to read // The upper bits of the physical pc - input logic [`XLEN-1:0] PCNextF, - input logic [`XLEN-1:0] PCPF, + input logic [`PA_BITS-1:0] PCNextF, + input logic [`PA_BITS-1:0] PCPF, // Signals to/from cache memory // The read coming out of it input logic [31:0] ICacheMemReadData, input logic ICacheMemReadValid, // The address at which we want to search the cache memory - output logic [`XLEN-1:0] PCTagF, - output logic [`XLEN-1:0] PCNextIndexF, + output logic [`PA_BITS-1:0] PCTagF, + output logic [`PA_BITS-1:0] PCNextIndexF, output logic ICacheReadEn, // Load data into the cache output logic ICacheMemWriteEnable, @@ -133,8 +133,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [`XLEN-1:0] PCPreFinalF, PCPFinalF, PCSpillF; - logic [`XLEN-1:OFFSETWIDTH] PCPTrunkF; + logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF; + logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; logic [31:0] FinalInstrRawF; @@ -156,11 +156,11 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // on spill we want to get the first 2 bytes of the next cache block. // the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can // simply add 2 to land on the next cache block. - assign PCSpillF = PCPF + `XLEN'b10; + assign PCPSpillF = PCPF + 2'b10; // *** modelsim does not allow the use of PA_BITS for literal width. // now we have to select between these three PCs assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary - assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF; + assign PCNextIndexF = PCMux[1] ? PCPSpillF : PCPreFinalF; // this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later. // *** read enable may not be necessary. @@ -170,11 +170,10 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( .d(PCMux), .q(PCMux_q)); - assign PCTagF = PCMux_q[1] ? PCSpillF : PCPF; - assign PCNextIndexF = PCPFinalF; + assign PCTagF = PCMux_q[1] ? PCPSpillF : PCPF; // truncate the offset from PCPF for memory address generation - assign PCPTrunkF = PCTagF[`XLEN-1:OFFSETWIDTH]; + assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH]; // Detect if the instruction is compressed assign CompressedF = FinalInstrRawF[1:0] != 2'b11; @@ -395,7 +394,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros. // fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with // more zeros after the addition. This will be the number of offset bits less the AHBByteLength. - logic [`XLEN-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; + logic [`PA_BITS-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}}; // verilator lint_off WIDTH diff --git a/wally-pipelined/src/cache/ICacheMem.sv b/wally-pipelined/src/cache/ICacheMem.sv index 4ea3d22a..9a5fdbe2 100644 --- a/wally-pipelined/src/cache/ICacheMem.sv +++ b/wally-pipelined/src/cache/ICacheMem.sv @@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) // If flush is high, invalidate the entire cache input logic flush, - input logic [`XLEN-1:0] PCTagF, // physical address - input logic [`XLEN-1:0] PCNextIndexF, // virtual address + input logic [`PA_BITS-1:0] PCTagF, // physical address + input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address input logic WriteEnable, input logic [BLOCKLEN-1:0] WriteLine, output logic [BLOCKLEN-1:0] ReadLineF, @@ -21,7 +21,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) localparam OFFSETLEN = $clog2(BLOCKBYTELEN); localparam INDEXLEN = $clog2(NUMLINES); // *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48 - localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN; + localparam TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; logic [TAGLEN-1:0] LookupTag; logic [NUMLINES-1:0] ValidOut; @@ -39,7 +39,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) cachetags (.*, .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .ReadData(LookupTag), - .WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]) + .WriteData(PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]) ); // Correctly handle the valid bits @@ -55,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) end DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]]; end - assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]); + assign HitF = DataValidBit && (LookupTag == PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]); endmodule diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index e3a0829b..907d30fa 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -31,8 +31,8 @@ module icache input logic clk, reset, input logic StallF, StallD, input logic FlushD, - input logic [`XLEN-1:0] PCNextF, - input logic [`XLEN-1:0] PCPF, + input logic [`PA_BITS-1:0] PCNextF, + input logic [`PA_BITS-1:0] PCPF, // Data read in from the ebu unit input logic [`XLEN-1:0] InstrInF, input logic InstrAckF, @@ -58,7 +58,7 @@ module icache logic ICacheMemWriteEnable; logic [BLOCKLEN-1:0] ICacheMemWriteData; logic EndFetchState; - logic [`XLEN-1:0] PCTagF, PCNextIndexF; + logic [`PA_BITS-1:0] PCTagF, PCNextIndexF; // Output signals from cache memory logic [31:0] ICacheMemReadData; logic ICacheMemReadValid; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index ca0071b1..275cee76 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -138,7 +138,9 @@ module ifu ( // jarred 2021-03-14 Add instrution cache block to remove rd2 assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live - icache icache(.*); + icache icache(.*, + .PCNextF(PCNextF[`PA_BITS-1:0]), + .PCPF(PCPFmmu));