From e1db967417780778d5f186d66459e41c70610901 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 6 Jan 2022 16:32:49 -0600
Subject: [PATCH 1/2] Clean up of cachefsm.

---
 pipelined/src/cache/cache.sv    |  9 +--------
 pipelined/src/cache/cachefsm.sv | 13 ++++++-------
 2 files changed, 7 insertions(+), 15 deletions(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index a7c5e623..f2d0b19e 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -243,15 +243,8 @@ module cache #(parameter integer LINELEN,
   assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0];
   assign FlushWayFlag = FlushWay[NUMWAYS-1];
 
-  // controller
-  // *** fixme
-  logic CacheableM;
-  
-  assign CacheableM = 1;
-
-
   cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, 
-					.RW, .Atomic, .CPUBusy, .CacheableM, .IgnoreRequest,
+					.RW, .Atomic, .CPUBusy, .IgnoreRequest,
  					.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, 
 					.CacheMiss, .CacheAccess, .SelAdr, .SetValid, 
 					.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable,
diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index b09f86a0..6201b82c 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -34,7 +34,6 @@ module cachefsm
    input logic 		  FlushCache,
    // hazard inputs
    input logic 		  CPUBusy,
-   input logic 		  CacheableM,
    // interlock fsm
    input logic 		  IgnoreRequest,
    // Bus inputs
@@ -100,8 +99,8 @@ module cachefsm
   assign AnyCPUReqM = |RW | (|Atomic);
 
   // outputs for the performance counters.
-  assign CacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
-  assign CacheMiss = CacheAccess & CacheableM & ~CacheHit;
+  assign CacheAccess = AnyCPUReqM & CurrState == STATE_READY;
+  assign CacheMiss = CacheAccess &  ~CacheHit;
 
   always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
@@ -159,7 +158,7 @@ module cachefsm
 		end
 		
 		// amo hit
-		else if(Atomic[1] & (&RW) & CacheableM & CacheHit) begin
+		else if(Atomic[1] & (&RW) & CacheHit) begin
 		  SelAdr = 2'b01;
 		  CacheStall = 1'b0;
 		  
@@ -175,7 +174,7 @@ module cachefsm
 		  end
 		end
 		// read hit valid cached
-		else if(RW[1] & CacheableM & CacheHit) begin
+		else if(RW[1] & CacheHit) begin
 		  CacheStall = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  
@@ -188,7 +187,7 @@ module cachefsm
 	      end
 		end
 		// write hit valid cached
-		else if (RW[0] & CacheableM & CacheHit) begin
+		else if (RW[0] & CacheHit) begin
 		  SelAdr = 2'b01;
 		  CacheStall = 1'b0;
 		  SRAMWordWriteEnable = 1'b1;
@@ -204,7 +203,7 @@ module cachefsm
 		  end
 		end
 		// read or write miss valid cached
-		else if((|RW) & CacheableM & ~CacheHit) begin
+		else if((|RW) & ~CacheHit) begin
 		  NextState = STATE_MISS_FETCH_WDV;
 		  CacheStall = 1'b1;
 		  CacheFetchLine = 1'b1;

From b3ebce0365b0847e0385856c935a650b0031e478 Mon Sep 17 00:00:00 2001
From: Katherine Parry <kparry4@gmail.com>
Date: Thu, 6 Jan 2022 23:03:20 +0000
Subject: [PATCH 2/2] some FPU test fixes

---
 addins/riscv-arch-test               |  2 +-
 pipelined/regression/Makefile        |  2 +-
 pipelined/regression/sim-wally       |  2 +-
 pipelined/regression/sim-wally-batch |  2 +-
 pipelined/src/fpu/fma.sv             | 10 +++-------
 pipelined/testbench/tests.vh         |  6 +++---
 6 files changed, 10 insertions(+), 14 deletions(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 307c77b2..be67c99b 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile
index 4dce61ab..ecebb246 100644
--- a/pipelined/regression/Makefile
+++ b/pipelined/regression/Makefile
@@ -23,4 +23,4 @@ make all:
 	# Link Linux test vectors (fix this later***)
 	#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
 
-	
\ No newline at end of file
+	
diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally
index 51c8b3ed..a7dffc9e 100755
--- a/pipelined/regression/sim-wally
+++ b/pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv64gc arch64d"
+vsim -do "do wally-pipelined.do rv32gc arch32f"
 
diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch
index 52b95c0c..7db25e6c 100755
--- a/pipelined/regression/sim-wally-batch
+++ b/pipelined/regression/sim-wally-batch
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv64gc arch64d 
+do wally-pipelined-batch.do rv32gc arch32f
 !
diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv
index d3881757..cc567fa3 100644
--- a/pipelined/src/fpu/fma.sv
+++ b/pipelined/src/fpu/fma.sv
@@ -557,7 +557,6 @@ module normalize(
     output logic [`NE+1:0]      SumExp,         // exponent of the normalized sum
     output logic                ResultDenorm    // is the result denormalized
 );
-    logic [`NE+1:0]     FracLen;            // length of the fraction
     logic [`NE+1:0]     SumExpTmp;          // exponent of the normalized sum not taking into account denormal or zero results
     logic [8:0]         DenormShift;        // right shift if the result is denormalized //***change this later
     logic [3*`NF+5:0]   CorrSumShifted;     // the shifted sum after LZA correction
@@ -574,9 +573,6 @@ module normalize(
     // Determine if the sum is zero
     assign SumZero = ~(|SumM);
 
-    // determine the length of the fraction based on precision
-    assign FracLen = FmtM ? `NF+1 : 13'd24;
-
     // calculate the sum's exponent
     assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
     assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}};
@@ -752,6 +748,7 @@ module fmaflags(
     output logic [4:0]          FMAFlgM // FMA flags
 );
     logic               SigNaN;     // is an input a signaling NaN
+    logic               GtMaxExp;   // is exponent greater than the maximum
     logic               UnderflowFlag, Inexact; // flags
 
     ///////////////////////////////////////////////////////////////////////////////
@@ -770,9 +767,8 @@ module fmaflags(
    
     // Set Overflow flag if the number is too big to be represented
     //      - Don't set the overflow flag if an overflowed result isn't outputed
-    logic LtMaxExp;
-    assign LtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[7:0] | FullResultExp[8];
-    assign Overflow = LtMaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
+    assign GtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[7:0] | FullResultExp[8];
+    assign Overflow = GtMaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
 
     // Set Underflow flag if the number is too small to be represented in normal numbers
     //      - Don't set the underflow flag if the result is exact
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index 53b464bf..6134f16d 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -1283,7 +1283,7 @@ string imperas32f[] = '{
     "rv32i_m/F/feq_b1-01", "6220",
     "rv32i_m/F/feq_b19-01", "a190",
     "rv32i_m/F/fle_b1-01", "6220",
-    "rv32i_m/F/fle_b19-01", "a190", // looks fine to me is the actual input value supposed to be infinity?
+    "rv32i_m/F/fle_b19-01", "a190",
     "rv32i_m/F/flt_b1-01", "6220",
     "rv32i_m/F/flt_b19-01", "8ee0", 
     "rv32i_m/F/flw-align-01", "2010",
@@ -1298,7 +1298,7 @@ string imperas32f[] = '{
     "rv32i_m/F/fmadd_b4-01", "3700",
     "rv32i_m/F/fmadd_b5-01", "3ac0",
     "rv32i_m/F/fmadd_b6-01", "3700",
-    //"rv32i_m/F/fmadd_b7-01", "d7f0", // input values aren't even in the memfile are being used in the test; didn't run even with fixed memfile
+    "rv32i_m/F/fmadd_b7-01", "37f0",
     "rv32i_m/F/fmadd_b8-01", "13f30", 
     "rv32i_m/F/fmax_b1-01", "7220",
     "rv32i_m/F/fmax_b19-01", "9e00",
@@ -1355,7 +1355,7 @@ string imperas32f[] = '{
     "rv32i_m/F/fnmsub_b17-01", "39d0",
     "rv32i_m/F/fnmsub_b18-01", "4d10", 
     "rv32i_m/F/fnmsub_b2-01", "4d60",
-    //"rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile
+    "rv32i_m/F/fnmsub_b3-01", "d4f0",
     "rv32i_m/F/fnmsub_b4-01", "3700",
     "rv32i_m/F/fnmsub_b5-01", "3ac0",
     "rv32i_m/F/fnmsub_b6-01", "3700",