diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 0f684358..f1c0b29f 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -77,10 +77,9 @@ module icache
   logic 		    FlushMem;
   logic 		    ICacheMemWriteEnable;
   logic [BLOCKLEN-1:0] 	    ICacheMemWriteData;
-  logic [`PA_BITS-1:0] 	    PCTagF, PCNextIndexF;  
+  logic [`PA_BITS-1:0] 	    PCTagF;  
   // Output signals from cache memory
   logic [31:0] 		    ICacheMemReadData;
-  logic 		    ICacheMemReadValid;
   logic 		    ICacheReadEn;
   logic [BLOCKLEN-1:0] 	    ReadLineF;
   
@@ -101,7 +100,6 @@ module icache
 
   logic 		       CntReset;
   logic [1:0] 		       SelAdr;
-  logic 		       SavePC;
   logic [INDEXLEN-1:0]	       RAdr;
   logic [NUMWAYS-1:0] 	       VictimWay;
   logic 		       LRUWriteEn;
@@ -302,7 +300,6 @@ module icache
 	     .CntEn,
 	     .CntReset,
 	     .SelAdr,
-    	     .SavePC,
 	     .LRUWriteEn
 	     );
 
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 49cbcb43..1d5ad0cd 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -61,7 +61,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
    output logic       CntEn,
    output logic       CntReset,
    output logic [1:0] SelAdr,
-   output logic       SavePC,
    output logic       LRUWriteEn
    );
 
@@ -117,6 +116,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
   statetype CurrState, NextState;
   logic 		       PreCntEn;
   logic 		       UnalignedSelect;
+  logic            SavePC; // unused right now *** consider deleting
 
   // the FSM is always runing, do not stall.
   always_ff @(posedge clk, posedge reset)
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index bdbf096d..0582395b 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -87,7 +87,7 @@ module ifu (
   logic             misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
   logic             PrivilegedChangePCM;
   logic             IllegalCompInstrD;
-  logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD;
+  logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
   logic [`XLEN-3:0] PCPlusUpperF;
   logic             CompressedF;
   logic [31:0]      InstrRawD, FinalInstrRawF;
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 5c8f1261..1b960488 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -45,7 +45,6 @@ module lsu
    input logic           FlushDCacheM,
    output logic 	       CommittedM, 
    output logic 	       SquashSCW,
-   output logic 	       DataMisalignedM,
    output logic 	       DCacheMiss,
    output logic 	       DCacheAccess,
 
@@ -94,6 +93,7 @@ module lsu
    );
 
   logic 		       DTLBPageFaultM;
+  logic 	         DataMisalignedM;
 
   
   logic [`PA_BITS-1:0] 	       MemPAdrM;  // from mmu to dcache
diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv
index d8839817..8c6614a1 100644
--- a/wally-pipelined/src/mmu/mmu.sv
+++ b/wally-pipelined/src/mmu/mmu.sv
@@ -80,7 +80,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
 );
 
   logic [`PA_BITS-1:0] TLBPAdr;
-  logic PMPSquashBusAccess, PMASquashBusAccess;
   // Translation lookaside buffer
 
   logic PMAInstrAccessFaultF, PMPInstrAccessFaultF;
diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv
index a95252f3..904dd0ee 100644
--- a/wally-pipelined/src/mmu/pmachecker.sv
+++ b/wally-pipelined/src/mmu/pmachecker.sv
@@ -32,12 +32,8 @@ module pmachecker (
 
   input  logic [`PA_BITS-1:0] PhysicalAddress,
   input  logic [1:0]          Size,
-
   input  logic        AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
-
   output logic        Cacheable, Idempotent, AtomicAllowed,
-  output logic        PMASquashBusAccess,
-
   output logic        PMAInstrAccessFaultF,
   output logic        PMALoadAccessFaultM,
   output logic        PMAStoreAccessFaultM
@@ -65,6 +61,5 @@ module pmachecker (
   assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
   assign PMALoadAccessFaultM  = ReadAccessM    && PMAAccessFault;
   assign PMAStoreAccessFaultM = WriteAccessM   && PMAAccessFault;
-  assign PMASquashBusAccess = PMAAccessFault;
 endmodule
 
diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv
index 11cb7ccb..06cc9ea8 100644
--- a/wally-pipelined/src/mmu/pmpchecker.sv
+++ b/wally-pipelined/src/mmu/pmpchecker.sv
@@ -41,11 +41,7 @@ module pmpchecker (
   // which we might not intend.
   input  var logic [7:0]   PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
   input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
-
   input  logic             ExecuteAccessF, WriteAccessM, ReadAccessM,
-
-  output logic             PMPSquashBusAccess,
-
   output logic             PMPInstrAccessFaultF,
   output logic             PMPLoadAccessFaultM,
   output logic             PMPStoreAccessFaultM
@@ -79,6 +75,6 @@ module pmpchecker (
   assign PMPStoreAccessFaultM = EnforcePMP && WriteAccessM   && ~|W;
   assign PMPLoadAccessFaultM  = EnforcePMP && ReadAccessM    && ~|R;
 
-  assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM;
+  //assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM;
 
 endmodule