From c72e2e5d49960421df0fc078ed5c304dd98aa770 Mon Sep 17 00:00:00 2001 From: cturek Date: Thu, 29 Sep 2022 23:08:27 +0000 Subject: [PATCH] Added integer inputs and flags to divsqrt --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 3 ++ pipelined/src/fpu/fpu.sv | 49 +++++++++++++---------- pipelined/src/wally/wallypipelinedcore.sv | 4 +- 3 files changed, 33 insertions(+), 23 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 43f7687c..3f6426a2 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -44,6 +44,9 @@ module fdivsqrt( input logic StallM, input logic StallE, input logic SqrtE, SqrtM, + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B + input logic [2:0] Funct3E, Funct3M, + input logic MDUE, W64E, output logic DivSM, output logic DivBusy, output logic DivDone, diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index b6eb25d2..459b891d 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -31,28 +31,30 @@ `include "wally-config.vh" module fpu ( - input logic clk, - input logic reset, - input logic [2:0] FRM_REGW, // Rounding mode (from CSR) - input logic [31:0] InstrD, // instruction (from IFU) - input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) - input logic [`XLEN-1:0] ForwardedSrcAE, // Integer input (from IEU) - input logic StallE, StallM, StallW, // stall signals (from HZU) - input logic FlushE, FlushM, FlushW, // flush signals (from HZU) - input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) - input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) - output logic FRegWriteM, // FP register write enable (to privileged unit) - output logic FpLoadStoreM, // Fp load instruction? (to LSU) - output logic FStallD, // Stall the decode stage (To HZU) - output logic FWriteIntE, // integer register write enable (to IEU) - output logic FCvtIntE, // Convert to int (to IEU) - output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) - output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) - output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) - output logic FCvtIntW, // select FCvtIntRes (to IEU) - output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU) - output logic IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit) - output logic [4:0] SetFflagsM // FPU flags (to privileged unit) + input logic clk, + input logic reset, + input logic [2:0] FRM_REGW, // Rounding mode (from CSR) + input logic [31:0] InstrD, // instruction (from IFU) + input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU) + input logic StallE, StallM, StallW, // stall signals (from HZU) + input logic FlushE, FlushM, FlushW, // flush signals (from HZU) + input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) + input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) + input logic [2:0] Funct3E, Funct3M, + input logic MDUE, W64E, + output logic FRegWriteM, // FP register write enable (to privileged unit) + output logic FpLoadStoreM, // Fp load instruction? (to LSU) + output logic FStallD, // Stall the decode stage (To HZU) + output logic FWriteIntE, // integer register write enable (to IEU) + output logic FCvtIntE, // Convert to int (to IEU) + output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) + output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) + output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) + output logic FCvtIntW, // select FCvtIntRes (to IEU) + output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU) + output logic IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit) + output logic [4:0] SetFflagsM // FPU flags (to privileged unit) ); // FPU specifics: @@ -259,8 +261,11 @@ module fpu ( // *** add other opperations fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE, + .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal .QmM, .DivDone(DivDoneM)); + + // // compare // - fmin/fmax // - flt/fle/feq diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 60d1f5f2..0f61f452 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -393,7 +393,9 @@ module wallypipelinedcore ( .STATUS_FS, // is floating-point enabled? .FRegWriteM, // FP register write enable .FpLoadStoreM, - .FStallD, // Stall the decode stage + .ForwardedSrcBE, // Integer input for intdiv + .Funct3E, .Funct3M, .MDUE, .W64E, // Integer flags and functions + .FStallD, // Stall the decode stage .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation .FWriteDataM, // Data to be written to memory .FIntResM, // data to be written to integer register