From c69a5dc8a646a54cd4f7859decb372d26ae7e425 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 21 Jul 2021 17:43:36 -0400 Subject: [PATCH] fixed issue with tlbflush remaining high during a stalled sfence instruction --- wally-pipelined/src/ifu/ifu.sv | 2 -- wally-pipelined/src/mmu/tlbcontrol.sv | 4 ++-- wally-pipelined/src/privileged/privileged.sv | 11 ++++++++++- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 946b3821..e79675c8 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -98,8 +98,6 @@ module ifu ( logic reset_q; // *** look at this later. logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; - - logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. diff --git a/wally-pipelined/src/mmu/tlbcontrol.sv b/wally-pipelined/src/mmu/tlbcontrol.sv index c0b41d94..1559d8e2 100644 --- a/wally-pipelined/src/mmu/tlbcontrol.sv +++ b/wally-pipelined/src/mmu/tlbcontrol.sv @@ -78,7 +78,7 @@ module tlbcontrol #(parameter ITLB = 0) ( endgenerate // Determine whether TLB is being used - assign TLBAccess = ReadAccess || WriteAccess; + assign TLBAccess = ReadAccess | WriteAccess; // Check whether upper bits of virtual addresss are all equal @@ -120,5 +120,5 @@ module tlbcontrol #(parameter ITLB = 0) ( endgenerate assign TLBHit = CAMHit & TLBAccess; - assign TLBMiss = ~CAMHit & ~TLBFlush & Translate & TLBAccess; + assign TLBMiss = (~CAMHit | TLBFlush) & Translate & TLBAccess; endmodule diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 3c605547..ce2daeba 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -102,6 +102,7 @@ module privileged ( logic STATUS_MIE, STATUS_SIE; logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW; logic md, sd; + logic StallMQ; /////////////////////////////////////////// @@ -157,8 +158,16 @@ module privileged ( assign BreakpointFaultM = ebreakM; // could have other causes too assign EcallFaultM = ecallM; - assign ITLBFlushF = sfencevmaM; + + flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ)); + assign ITLBFlushF = sfencevmaM & ~StallMQ; assign DTLBFlushM = sfencevmaM; + // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction + // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program. + // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and + // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush + // after a cycle AND pulse it for another cycle on any further back-to-back sfences. + // A page fault might occur because of insufficient privilege during a TLB // lookup or a improperly formatted page table during walking