From 526aff54a86abfd7f6d377459132d2bc362ae76c Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 1 Nov 2021 14:09:49 -0700 Subject: [PATCH 01/21] linux testgen refactor --- .gitignore | 26 +- .../buildroot-config-src/busybox.config | 0 .../buildroot-config-src/linux.config | 0 .../buildroot-config-src/main.config | 0 .../buildroot-config-src/make-buildroot.sh | 0 .../linux-testvectors/tvCopier.py | 0 .../linux-testvectors/tvLinker.sh | 0 .../linux-testvectors/tvUnlinker.sh | 0 .../testvector-generation/analyzeTrace.py | 0 .../testvector-generation/analyzeTrace.sh | 0 .../testvector-generation/combineGDBs.py | 0 .../testvector-generation/debug.gdb | 0 .../testvector-generation/debug.sh | 1 + .../testvector-generation/fix_mem.py | 0 .../testvector-generation/genCheckpoint.gdb | 0 .../testvector-generation/genCheckpoint.sh | 2 +- .../testvector-generation/genInitMem.gdb | 0 .../testvector-generation/genInitMem.sh | 0 .../testvector-generation/genSettings.sh | 0 .../testvector-generation/genTrace.gdb | 0 .../testvector-generation/genTrace.sh | 0 .../testvector-generation/parseGDBtoTrace.py | 0 .../testvector-generation/parseQemuToGDB.py | 0 .../testvector-generation/parseState.py | 0 .../testvector-generation/remove_dup.awk | 0 .../config/buildroot/wally-config.vh | 7 +- .../config/busybear/BTBPredictor.txt | 1024 ----------------- .../config/busybear/twoBitPredictor.txt | 1024 ----------------- .../config/busybear/wally-config.vh | 127 -- .../linux-testgen/WALLY-README-UPDATES.txt | 38 - .../linux-testgen/WALLY-README.txt | 57 - .../intermediate-outputs/git_create_dir.txt | 1 - 32 files changed, 14 insertions(+), 2293 deletions(-) rename {wally-pipelined => tests}/linux-testgen/buildroot-config-src/busybox.config (100%) rename {wally-pipelined => tests}/linux-testgen/buildroot-config-src/linux.config (100%) rename {wally-pipelined => tests}/linux-testgen/buildroot-config-src/main.config (100%) rename {wally-pipelined => tests}/linux-testgen/buildroot-config-src/make-buildroot.sh (100%) rename {wally-pipelined => tests}/linux-testgen/linux-testvectors/tvCopier.py (100%) rename {wally-pipelined => tests}/linux-testgen/linux-testvectors/tvLinker.sh (100%) rename {wally-pipelined => tests}/linux-testgen/linux-testvectors/tvUnlinker.sh (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/analyzeTrace.py (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/analyzeTrace.sh (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/combineGDBs.py (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/debug.gdb (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/debug.sh (98%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/fix_mem.py (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/genCheckpoint.gdb (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/genCheckpoint.sh (98%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/genInitMem.gdb (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/genInitMem.sh (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/genSettings.sh (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/genTrace.gdb (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/genTrace.sh (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/parseGDBtoTrace.py (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/parseQemuToGDB.py (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/parseState.py (100%) rename {wally-pipelined => tests}/linux-testgen/testvector-generation/remove_dup.awk (100%) delete mode 100644 wally-pipelined/config/busybear/BTBPredictor.txt delete mode 100644 wally-pipelined/config/busybear/twoBitPredictor.txt delete mode 100644 wally-pipelined/config/busybear/wally-config.vh delete mode 100644 wally-pipelined/linux-testgen/WALLY-README-UPDATES.txt delete mode 100644 wally-pipelined/linux-testgen/WALLY-README.txt delete mode 100644 wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/git_create_dir.txt diff --git a/.gitignore b/.gitignore index 501874d0..2542dd88 100644 --- a/.gitignore +++ b/.gitignore @@ -19,27 +19,19 @@ wlft* /imperas-riscv-tests/FunctionRadix.addr /imperas-riscv-tests/ProgramMap.txt /imperas-riscv-tests/logs -/wally-pipelined/linux-testgen/qemu_output.txt -/wally-pipelined/linux-testgen/qemu_in_gdb_format.txt *.o *.d testsBP/*/*/*.elf* testsBP/*/OBJ/* testsBP/*/*.a -wally-pipelined/linux-testgen/linux-testvectors/* -wally-pipelined/linux-testgen/nohup* -wally-pipelined/linux-testgen/x* -!wally-pipelined/linux-testgen/linux-testvectors/tvCopier.py -!wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh -!wally-pipelined/linux-testgen/linux-testvectors/tvUnlinker.sh -!wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs -wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/* -!wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/git_create_dir.txt -wally-pipelined/linux-testgen/buildroot/ -wally-pipelined/linux-testgen/buildroot-image-output -wally-pipelined/linux-testgen/buildroot-config-src/main.config.old -wally-pipelined/linux-testgen/buildroot-config-src/linux.config.old -wally-pipelined/linux-testgen/buildroot-config-src/busybox.config.old +tests/linux-testgen/linux-testvectors/* +!tests/linux-testgen/linux-testvectors/tvCopier.py +!tests/linux-testgen/linux-testvectors/tvLinker.sh +!tests/linux-testgen/linux-testvectors/tvUnlinker.sh +tests/linux-testgen/buildroot +tests/linux-testgen/buildroot-image-output +tests/linux-testgen/buildroot-config-src/main.config.old +tests/linux-testgen/buildroot-config-src/linux.config.old +tests/linux-testgen/buildroot-config-src/busybox.config.old wally-pipelined/regression/slack-notifier/slack-webhook-url.txt wally-pipelined/regression/logs - diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/busybox.config b/tests/linux-testgen/buildroot-config-src/busybox.config similarity index 100% rename from wally-pipelined/linux-testgen/buildroot-config-src/busybox.config rename to tests/linux-testgen/buildroot-config-src/busybox.config diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/tests/linux-testgen/buildroot-config-src/linux.config similarity index 100% rename from wally-pipelined/linux-testgen/buildroot-config-src/linux.config rename to tests/linux-testgen/buildroot-config-src/linux.config diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/main.config b/tests/linux-testgen/buildroot-config-src/main.config similarity index 100% rename from wally-pipelined/linux-testgen/buildroot-config-src/main.config rename to tests/linux-testgen/buildroot-config-src/main.config diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/make-buildroot.sh b/tests/linux-testgen/buildroot-config-src/make-buildroot.sh similarity index 100% rename from wally-pipelined/linux-testgen/buildroot-config-src/make-buildroot.sh rename to tests/linux-testgen/buildroot-config-src/make-buildroot.sh diff --git a/wally-pipelined/linux-testgen/linux-testvectors/tvCopier.py b/tests/linux-testgen/linux-testvectors/tvCopier.py similarity index 100% rename from wally-pipelined/linux-testgen/linux-testvectors/tvCopier.py rename to tests/linux-testgen/linux-testvectors/tvCopier.py diff --git a/wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh b/tests/linux-testgen/linux-testvectors/tvLinker.sh similarity index 100% rename from wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh rename to tests/linux-testgen/linux-testvectors/tvLinker.sh diff --git a/wally-pipelined/linux-testgen/linux-testvectors/tvUnlinker.sh b/tests/linux-testgen/linux-testvectors/tvUnlinker.sh similarity index 100% rename from wally-pipelined/linux-testgen/linux-testvectors/tvUnlinker.sh rename to tests/linux-testgen/linux-testvectors/tvUnlinker.sh diff --git a/wally-pipelined/linux-testgen/testvector-generation/analyzeTrace.py b/tests/linux-testgen/testvector-generation/analyzeTrace.py similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/analyzeTrace.py rename to tests/linux-testgen/testvector-generation/analyzeTrace.py diff --git a/wally-pipelined/linux-testgen/testvector-generation/analyzeTrace.sh b/tests/linux-testgen/testvector-generation/analyzeTrace.sh similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/analyzeTrace.sh rename to tests/linux-testgen/testvector-generation/analyzeTrace.sh diff --git a/wally-pipelined/linux-testgen/testvector-generation/combineGDBs.py b/tests/linux-testgen/testvector-generation/combineGDBs.py similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/combineGDBs.py rename to tests/linux-testgen/testvector-generation/combineGDBs.py diff --git a/wally-pipelined/linux-testgen/testvector-generation/debug.gdb b/tests/linux-testgen/testvector-generation/debug.gdb similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/debug.gdb rename to tests/linux-testgen/testvector-generation/debug.gdb diff --git a/wally-pipelined/linux-testgen/testvector-generation/debug.sh b/tests/linux-testgen/testvector-generation/debug.sh similarity index 98% rename from wally-pipelined/linux-testgen/testvector-generation/debug.sh rename to tests/linux-testgen/testvector-generation/debug.sh index fc5549a2..e6c96f8b 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/debug.sh +++ b/tests/linux-testgen/testvector-generation/debug.sh @@ -5,6 +5,7 @@ tcpPort=1237 # Run without GDB ($customQemu \ -M virt \ +-m 128M \ -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on) diff --git a/wally-pipelined/linux-testgen/testvector-generation/fix_mem.py b/tests/linux-testgen/testvector-generation/fix_mem.py similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/fix_mem.py rename to tests/linux-testgen/testvector-generation/fix_mem.py diff --git a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.gdb b/tests/linux-testgen/testvector-generation/genCheckpoint.gdb similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.gdb rename to tests/linux-testgen/testvector-generation/genCheckpoint.gdb diff --git a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh b/tests/linux-testgen/testvector-generation/genCheckpoint.sh similarity index 98% rename from wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh rename to tests/linux-testgen/testvector-generation/genCheckpoint.sh index fc22dd28..4883ef3f 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh +++ b/tests/linux-testgen/testvector-generation/genCheckpoint.sh @@ -3,7 +3,7 @@ source genSettings.sh tcpPort=1236 -instrs=480000000 +instrs=450000000 checkOutDir="$outDir/checkpoint$instrs" checkIntermedDir="$checkOutDir/intermediate-outputs" diff --git a/wally-pipelined/linux-testgen/testvector-generation/genInitMem.gdb b/tests/linux-testgen/testvector-generation/genInitMem.gdb similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/genInitMem.gdb rename to tests/linux-testgen/testvector-generation/genInitMem.gdb diff --git a/wally-pipelined/linux-testgen/testvector-generation/genInitMem.sh b/tests/linux-testgen/testvector-generation/genInitMem.sh similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/genInitMem.sh rename to tests/linux-testgen/testvector-generation/genInitMem.sh diff --git a/wally-pipelined/linux-testgen/testvector-generation/genSettings.sh b/tests/linux-testgen/testvector-generation/genSettings.sh similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/genSettings.sh rename to tests/linux-testgen/testvector-generation/genSettings.sh diff --git a/wally-pipelined/linux-testgen/testvector-generation/genTrace.gdb b/tests/linux-testgen/testvector-generation/genTrace.gdb similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/genTrace.gdb rename to tests/linux-testgen/testvector-generation/genTrace.gdb diff --git a/wally-pipelined/linux-testgen/testvector-generation/genTrace.sh b/tests/linux-testgen/testvector-generation/genTrace.sh similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/genTrace.sh rename to tests/linux-testgen/testvector-generation/genTrace.sh diff --git a/wally-pipelined/linux-testgen/testvector-generation/parseGDBtoTrace.py b/tests/linux-testgen/testvector-generation/parseGDBtoTrace.py similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/parseGDBtoTrace.py rename to tests/linux-testgen/testvector-generation/parseGDBtoTrace.py diff --git a/wally-pipelined/linux-testgen/testvector-generation/parseQemuToGDB.py b/tests/linux-testgen/testvector-generation/parseQemuToGDB.py similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/parseQemuToGDB.py rename to tests/linux-testgen/testvector-generation/parseQemuToGDB.py diff --git a/wally-pipelined/linux-testgen/testvector-generation/parseState.py b/tests/linux-testgen/testvector-generation/parseState.py similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/parseState.py rename to tests/linux-testgen/testvector-generation/parseState.py diff --git a/wally-pipelined/linux-testgen/testvector-generation/remove_dup.awk b/tests/linux-testgen/testvector-generation/remove_dup.awk similarity index 100% rename from wally-pipelined/linux-testgen/testvector-generation/remove_dup.awk rename to tests/linux-testgen/testvector-generation/remove_dup.awk diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 5ccac7de..6b4ccb82 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -31,8 +31,7 @@ `define BUILDROOT 1 `define BUSYBEAR 0 `define LINUX_FIX_READ {'h10000005} -`define LINUX_TEST_VECTORS "../linux-testgen/linux-testvectors/" -//`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/" +`define LINUX_TEST_VECTORS "../../tests/linux-testgen/linux-testvectors/" // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 @@ -114,8 +113,8 @@ `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 4 -`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt" +`define TWO_BIT_PRELOAD "../config/buildroot/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/buildroot/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/wally-pipelined/config/busybear/BTBPredictor.txt b/wally-pipelined/config/busybear/BTBPredictor.txt deleted file mode 100644 index b761147c..00000000 --- a/wally-pipelined/config/busybear/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 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-00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh deleted file mode 100644 index 9ab21bae..00000000 --- a/wally-pipelined/config/busybear/wally-config.vh +++ /dev/null @@ -1,127 +0,0 @@ -////////////////////////////////////////// -// busybear-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 1 -`define LINUX_FIX_READ {'h10000005} -`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/" -//`define LINUX_TEST_VECTORS "../../../busybear_boot/" -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -`define MISA (32'h0014112D) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define ZICOUNTERS_SUPPORTED 1 -`define COUNTERS 32 -`define DESIGN_COMPILER 0 - -// Microarchitectural Features -`define UARCH_PIPELINED 1 -`define UARCH_SUPERSCALR 0 -`define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 1 -`define MEM_DTIM 1 -`define MEM_ICACHE 1 -`define MEM_VIRTMEM 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 2048 -`define DCACHE_BLOCKLENINBITS 256 -`define DCACHE_REPLBITS 3 -`define ICACHE_NUMWAYS 1 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 - -// Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 - -// Address space -`define RESET_VECTOR 64'h0000000000001000 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -`define BOOTTIM_SUPPORTED 1'b1 -//`define BOOTTIM_BASE 56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIM_RANGE 56'h00003FFF -`define BOOTTIM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIM_RANGE 56'h00000FFF -`define TIM_SUPPORTED 1'b1 -`define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10012000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF - -// Bus Interface width -`define AHBW 64 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 - -// Hardware configuration -//`define UART_PRESCALE 1 -`define UART_PRESCALE 0 - -// Interrupt configuration -`define PLIC_NUM_SRC 53 -`define PLIC_UART_ID 4 - -`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt" -`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE -`define BPRED_ENABLED 1 - - - diff --git a/wally-pipelined/linux-testgen/WALLY-README-UPDATES.txt b/wally-pipelined/linux-testgen/WALLY-README-UPDATES.txt deleted file mode 100644 index a3c0390b..00000000 --- a/wally-pipelined/linux-testgen/WALLY-README-UPDATES.txt +++ /dev/null @@ -1,38 +0,0 @@ -Many of the scripts to build the linux ram.txt and trace files have changed over the Summer. -Specifically the parsed*.txt files have all been replaced by a single all.txt file which contains -all of the changes concurrent with a specific instruction. -Each line of all.txt is encoded in the following way. - -The tokens are space deliminted (limitation the parsing function in system verilog). This could be -improved with some effort. - - denotes a required token. - -()? is an optional set of tokens. Exactly 0 or 1 of this pattern will occur. -The register update, memory operation, and CSR update are all possilbe but not present on all operations. -()+ is used to denote a variable number of this pattern with at least 1 instance of the pattern. -All integers are in hex and not zero extended. - - ( )? (
)? ( ( )+)? - -Example - -1010 182b283 ld_t0,24(t0) GPR 5 80000000 MemR 1018 0 80000000 - -PC = 0x1010 -Instruction encoding = 0x182_b283 -instruction pneumonic (text) = ld_t0,24(t0) -Updating x5 to 0x8000_0000 -Memory read at address 0x8000_0000 with read data of 0x8000_0000 - -CSR updates can occur in more than once for a single instruction. The multiple sets will appear as pairs of regsiter name followed by value. - -**** This trace is generated using the CreateTrace.sh script. - -Generation of ram.txt has not changed. Still use logBuildrootMem.sh - -Only the all.txt and ram.txt are required to run modelsim's linux simulation. However there are three additional files will aid -in the debugging process. logBuildrootMem.sh was modified to also create an object dump from the vmlinux image. Using -extractFunctionRadix.sh the objdump is converted into two files vmlinux.objdump.addr and vmlinux.objdump.lab which contain -the addresses and labels of global functions in the linux binarary. The linux test bench is configured to uses these two files -to tell the user which function is currently being executed in modelsim. diff --git a/wally-pipelined/linux-testgen/WALLY-README.txt b/wally-pipelined/linux-testgen/WALLY-README.txt deleted file mode 100644 index 5e1228a0..00000000 --- a/wally-pipelined/linux-testgen/WALLY-README.txt +++ /dev/null @@ -1,57 +0,0 @@ -If you do not need to update the Linux image, then go to ./linux-testvectors and -use tvCopier.py or tvLinker.sh to copy/link premade RAMs and testvectors from Tera. -The RAMs are needed for Wally to run the Linux code, and the testvectors are needed -to verify Wally is executing the code correctly. - -If you instead wish to regenerate the RAMs and testvectors from a new Linux image, -you'll need to build the new Linux image, simulate it, and parse its output, -as described below. - -*To build a new Linux image: - 1. Git clone the Buildroot repository to ./buildroot: - git clone https://github.com/buildroot/buildroot.git - For reference, Wally (*** will) be proven to work on an image built using - Buildroot when the following was the most recent commit to the Buildroot repo: - commit 4047e10ed6e20492bae572d4929eaa5d67eed746 - Author: Gwenhael Goavec-Merou - Date: Wed Jun 30 06:27:10 2021 +0200 - - 2. If you wish to modify the configs, then in ./buildroot: - a. Run "make menuconfig" or "make linux-menuconfig" or "make busybox-menuconfig". - b. Use the TUI (terminal UI) to load in the existing configs. - - For menuconfig, you can load in the source file from - "../buildroot-config-src/main.config" - - For linux-menuconfig or busybox-menuconfig, load in from - "../../../../buildroot-config-src/.config" - because for linux and busybox, make traverses down to - ./buildroot/output/build/. - - One annoying thing about the TUI is that if it has a path already loaded, - then before you can enter the new path to buildroot-config-src, you need to - delete the existing one from the textbox. Doing so requires more than backspace. - Once you've deleted as much of the existing path as you can see, arrow left to - check if there is more text you need to delete. - - c. Likewise, when you are done editing, tell the TUI to save to the same location. - - 3. Finally go to ./buildroot-config-src and run make-buildroot.sh. - This script copies ./buildroot-config-src/main.config to ./buildroot/.config - and then invokes make. This is clumsy but effective because buildroot - sometimes does weird things to .config, like moving it to .config.old and - making a new .config -- doing so can really mess up symbolic/hard links. - - 4. If you'd like debugging symbols, then reconfigure Buildroot to output "vmlinux" - and run make-buildroot again. - -*To generate new RAMs and testvectors from a Linux image: - 1. sym link ./buildroot-image-output to either your new image in ./buildroot/output/image - or the existing image at /courses/e190ax/buildroot-image-output on Tera. - This might require first deleting the empty buildroot-image-output directory. - 2. Then run ./testvector-generation/logBuildrootMem.sh to generate RAMs. - 3. Then run ./testvector-generation/logAllBuildroot.sh to generate testvectors. - - These latter two steps require QEMU. - Note that you can only have one instance of QEMU open at a time! - At least on Tera, it seems. Check "ps -ef" to see if anybody else is running QEMU. diff --git a/wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/git_create_dir.txt b/wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/git_create_dir.txt deleted file mode 100644 index 8b0068e8..00000000 --- a/wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/git_create_dir.txt +++ /dev/null @@ -1 +0,0 @@ -This file only exists so that git will create ./. From 9fe8820ed0966f7baa9ed43d0134e4092c027b16 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 1 Nov 2021 15:31:38 -0700 Subject: [PATCH 02/21] genCheckpoint syntax fix --- tests/linux-testgen/testvector-generation/genCheckpoint.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/linux-testgen/testvector-generation/genCheckpoint.sh b/tests/linux-testgen/testvector-generation/genCheckpoint.sh index 4883ef3f..cca7486e 100755 --- a/tests/linux-testgen/testvector-generation/genCheckpoint.sh +++ b/tests/linux-testgen/testvector-generation/genCheckpoint.sh @@ -32,7 +32,7 @@ then # Post-Process GDB outputs ./parseState.py "$checkOutDir" ./fix_mem.py "$checkIntermedDir/ramGDB.txt" "$checkOutDir/ram.txt" - tail -n+$($instrs+1) "$outDir/$traceFile" > "$checkOutDir/$traceFile" + tail -n+$(($instrs+1)) "$outDir/$traceFile" > "$checkOutDir/$traceFile" else echo "You can change the number of instructions by editing the \"instrs\" variable in this script." echo "Have a nice day!" From 0c7681b942b8f5816a4123d2302b3d93ce14cbe3 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 2 Nov 2021 21:19:12 -0700 Subject: [PATCH 03/21] fix testbench interrupt timing --- wally-pipelined/regression/linux-wave.do | 39 +-- wally-pipelined/testbench/testbench-linux.sv | 302 ++++++++++++------- 2 files changed, 210 insertions(+), 131 deletions(-) diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do index 30c2b036..d2350d0e 100644 --- a/wally-pipelined/regression/linux-wave.do +++ b/wally-pipelined/regression/linux-wave.do @@ -60,20 +60,26 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -group {WriteBack stage} /testbench/PCW -add wave -noupdate -group {WriteBack stage} /testbench/InstrW -add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW -add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -expand -group {Execution Stage} /testbench/textE +add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName +add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/textM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW +add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW +add wave -noupdate -expand -group {WriteBack stage} /testbench/ExpectedPCW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName +add wave -noupdate -expand -group {WriteBack stage} /testbench/textW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -484,7 +490,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/p add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/line add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW @@ -510,7 +515,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0} +WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {5672440 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -526,4 +531,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {182 ns} {330 ns} +WaveRestoreZoom {5672937 ns} {5673085 ns} diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 72adf589..72061f9e 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -103,30 +103,35 @@ module testbench(); string checkpointDir; logic [1:0] initPriv; // Signals used to parse the trace file - integer data_file_all; - string name; - integer matchCount; - string line; - logic [`XLEN-1:0] ExpectedPCM; - logic [31:0] ExpectedInstrM; - string textM; - string token; - string ExpectedTokens [31:0]; - integer index; - integer StartIndex, EndIndex; - integer TokenIndex; - integer MarkerIndex; - integer NumCSRM; + `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \ + integer traceFile``STAGE; \ + integer matchCount``STAGE; \ + string line``STAGE; \ + string token``STAGE; \ + string ExpectedTokens``STAGE [31:0]; \ + integer index``STAGE; \ + integer StartIndex``STAGE, EndIndex``STAGE; \ + integer TokenIndex``STAGE; \ + integer MarkerIndex``STAGE; \ + integer NumCSR``STAGE; \ + logic [`XLEN-1:0] ExpectedPC``STAGE; \ + logic [31:0] ExpectedInstr``STAGE; \ + string text``STAGE; \ + string MemOp``STAGE; \ + string RegWrite``STAGE; \ + integer ExpectedRegAdr``STAGE; \ + logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ + logic [`XLEN-1:0] ExpectedMemAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ + string ExpectedCSRArray``STAGE[10:0]; \ + logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; + `DECLARE_TRACE_SCANNER_SIGNALS(E) + `DECLARE_TRACE_SCANNER_SIGNALS(M) + integer NextMIPexpected; + integer NextMepcExpected; // Memory stage expected values from trace logic checkInstrM; integer MIPexpected; - string RegWriteM; - integer ExpectedRegAdrM; - logic [`XLEN-1:0] ExpectedRegValueM; - string MemOpM; - logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM; - string ExpectedCSRArrayM[10:0]; - logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0]; + string name; logic [`AHBW-1:0] readDataExpected; // Write back stage expected values from trace logic checkInstrW; @@ -148,6 +153,11 @@ module testbench(); integer NumCSRPostWIndex; logic [`XLEN-1:0] InstrCountW; integer RequestDelayedMIP; + integer ForceMIPFuture; + integer CSRIndex; + longint MepcExpected; + integer CheckMIPFutureE; + integer CheckMIPFutureM; // Useful Aliases `define RF dut.hart.ieu.dp.regf.rf `define PC dut.hart.ifu.pcreg.q @@ -292,13 +302,15 @@ module testbench(); ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"}; if (CHECKPOINT==0) begin // normal $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); - data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); + traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); + traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); InstrCountW = '0; end else begin // checkpoint $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT); checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir}; $readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM); - data_file_all = $fopen({checkpointDir,"all.txt"}, "r"); + traceFileE = $fopen({checkpointDir,"all.txt"}, "r"); + traceFileM = $fopen({checkpointDir,"all.txt"}, "r"); InstrCountW = CHECKPOINT; // manual checkpoint initializations that don't neatly fit into MACRO force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17]; @@ -319,8 +331,12 @@ module testbench(); release `INSTRET; release `CURR_PRIV; end + // Get the E-stage trace reader ahead of the M-stage trace reader + matchCountE = $fgets(lineE,traceFileE); end + + /////////////////////////////////////////////////////////////////////////////// //////////////////////////////////// CORE ///////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// @@ -332,94 +348,158 @@ module testbench(); // on the next falling edge the expected state is compared to the wally state. // step 0: read the expected state - assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM; + assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM; + `define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \ + // always check PC, instruction bits \ + if (checkInstrM) begin \ + // read 1 line of the trace file \ + matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \ + if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ + // extract PC, Instr \ + matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \ + \ + // for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. \ + // strtok was the best idea but it cannot be used correctly as system verilog does not have null \ + // terminated strings. \ + \ + // Just going to do this char by char. \ + StartIndex``STAGE = 0; \ + TokenIndex``STAGE = 0; \ + //$display("len = %d", line``STAGE.len()); \ + for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \ + //$display("char = %s", line``STAGE[index]); \ + if (line``STAGE[index``STAGE] == " " || line``STAGE[index``STAGE] == "\n") begin \ + EndIndex``STAGE = index``STAGE; \ + ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \ + //$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \ + StartIndex``STAGE = EndIndex``STAGE + 1; \ + TokenIndex``STAGE++; \ + end \ + end \ + \ + MarkerIndex``STAGE = 3; \ + NumCSR``STAGE = 0; \ + MemOp``STAGE = ""; \ + RegWrite``STAGE = ""; \ + \ + #2; \ + \ + while(TokenIndex``STAGE > MarkerIndex``STAGE) begin \ + // parse the GPR \ + if (ExpectedTokens``STAGE[MarkerIndex``STAGE] == "GPR") begin \ + RegWrite``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%d", ExpectedRegAdr``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedRegValue``STAGE); \ + MarkerIndex``STAGE += 3; \ + // parse memory address, read data, and/or write data \ + end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \ + MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedMemAdr``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \ + MarkerIndex``STAGE += 4; \ + // parse CSRs, because there are 1 or more CSRs after the CSR token \ + // we check if the CSR token or the number of CSRs is greater than 0. \ + // if so then we want to parse for a CSR. \ + end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" || NumCSR``STAGE > 0) begin \ + if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR") begin \ + // all additional CSR's won't have this token. \ + MarkerIndex``STAGE++; \ + end \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE], "%s", ExpectedCSRArray``STAGE[NumCSR``STAGE]); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedCSRArrayValue``STAGE[NumCSR``STAGE]); \ + MarkerIndex``STAGE += 2; \ + if(`"STAGE`"=="E") begin \ + // match MIP to QEMU's because interrupts are imprecise \ + if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "mip") begin \ + CheckMIPFutureE = 1; \ + NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \ + end \ + // $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); \ + // $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); \ + // // if PC does not equal MEPC, request delayed MIP is True \ + // if(ExpectedPCM != ExpectedCSRArrayM[7]) begin \ + // RequestDelayedMIP = 1; \ + // end else begin \ + // $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); \ + // MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; \ + // force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; \ + // end \ + // end \ + // $display("%tns: ExpectedCSRArrayM::: %p",$time,ExpectedCSRArrayM); \ + if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \ + $display("hello! we are here."); \ + MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \ + $display("%tns: MepcExpected: %x",$time,MepcExpected); \ + end \ + end \ + \ + NumCSR``STAGE++; \ + end \ + end \ + if(`"STAGE`"=="M") begin \ + // override on special conditions \ + if (ExpectedMemAdrM == 'h10000005) begin \ + //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); \ + force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ + end \ + if(textM.substr(0,5) == "rdtime") begin \ + //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); \ + force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ + end \ + end \ + end \ + always @(negedge clk) begin - // always check PC, instruction bits - if (checkInstrM) begin - // read 1 line of the trace file - matchCount = $fgets(line, data_file_all); - if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line); - // extract PC, Instr - matchCount = $sscanf(line, "%x %x %s", ExpectedPCM, ExpectedInstrM, textM); - //$display("matchCount %d, PCM %x ExpectedInstrM %x textM %x", matchCount, ExpectedPCM, ExpectedInstrM, textM); + `SCAN_NEW_INSTR_FROM_TRACE(E) + end - // for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. - // strtok was the best idea but it cannot be used correctly as system verilog does not have null - // terminated strings. - - // Just going to do this char by char. - StartIndex = 0; - TokenIndex = 0; - //$display("len = %d", line.len()); - for(index = 0; index < line.len(); index++) begin - //$display("char = %s", line[index]); - if (line[index] == " " || line[index] == "\n") begin - EndIndex = index; - ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1); - //$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1)); - StartIndex = EndIndex + 1; - TokenIndex++; - end + always @(negedge clk) begin + `SCAN_NEW_INSTR_FROM_TRACE(M) + end + + // MIP spoofing + always @(posedge clk) begin + #1; + if(CheckMIPFutureE) CheckMIPFutureE <= 0; + CheckMIPFutureM <= CheckMIPFutureE; + if(CheckMIPFutureM) begin + if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin + RequestDelayedMIP = 1; + $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); + end else begin // update MIP immediately + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; end - - MarkerIndex = 3; - NumCSRM = 0; - MemOpM = ""; - RegWriteM = ""; - - #2; - - while(TokenIndex > MarkerIndex) begin - // parse the GPR - if (ExpectedTokens[MarkerIndex] == "GPR") begin - RegWriteM = ExpectedTokens[MarkerIndex]; - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM); - MarkerIndex += 3; - // parse memory address, read data, and/or write data - end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin - MemOpM = ExpectedTokens[MarkerIndex]; - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM); - MarkerIndex += 4; - // parse CSRs, because there are 1 or more CSRs after the CSR token - // we check if the CSR token or the number of CSRs is greater than 0. - // if so then we want to parse for a CSR. - end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin - if(ExpectedTokens[MarkerIndex] == "CSR") begin - // all additional CSR's won't have this token. - MarkerIndex++; - end - matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]); - MarkerIndex += 2; - // match MIP to QEMU's because interrupts are imprecise - if(ExpectedCSRArrayM[NumCSRM].substr(0, 2) == "mip") begin - $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); - $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); - // if PC does not equal MEPC, request delayed MIP is True - if(ExpectedPCM != ExpectedCSRArrayM[7]) begin - RequestDelayedMIP = 1; - end else begin - $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); - MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; - force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; - end - end - NumCSRM++; - end - end - // override on special conditions - if (ExpectedMemAdrM == 'h10000005) begin - //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); - force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; - end - if(textM.substr(0,5) == "rdtime") begin - //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); - force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; + $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM); + $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM); + $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM); + $display("%tn: MepcExpected = %x",$time,MepcExpected); + $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); + // if PC does not equal MEPC, request delayed MIP is True + $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM)); + $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]); + $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]); + + if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin + RequestDelayedMIP = 1; + $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); + end else begin + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; end end + if(RequestDelayedMIP) begin + $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + $display("%tns: MepcExpected %x",$time,MepcExpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; + $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); + RequestDelayedMIP = 0; + end end // step 1: register expected state into the write back stage. @@ -449,7 +529,7 @@ module testbench(); ExpectedMemWriteDataW <= '0; ExpectedMemReadDataW <= '0; NumCSRW <= '0; - end else begin + end else if (dut.hart.ieu.c.InstrValidM) begin ExpectedPCW <= ExpectedPCM; ExpectedInstrW <= ExpectedInstrM; textW <= textM; @@ -484,12 +564,6 @@ module testbench(); // step2: make all checks in the write back stage. assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. always @(negedge clk) begin - if(RequestDelayedMIP) begin - $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]); - MIPexpected = ExpectedCSRArrayValueW[NumCSRM]; - force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; - RequestDelayedMIP = 0; - end // always check PC, instruction bits if (checkInstrW) begin InstrCountW += 1; @@ -521,7 +595,7 @@ module testbench(); if(MemOpW == "MemR" || MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW); `checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin + end else if(MemOpW == "MemW" || MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) end From f7642a282d3d267691f90dd3676a65d05709e590 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 3 Nov 2021 01:50:00 -0700 Subject: [PATCH 04/21] edited to include missing instructions added cd tests before cd imperas-riscv-tests to reflect new tests folder modified cd ../addins so we can point to it from the new imperas-riscv-tests within the tests folder added instructions so the buildroot test exists --- README.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 975b8f14..36fbbb4f 100644 --- a/README.md +++ b/README.md @@ -8,9 +8,10 @@ To use Wally on Linux: ``` git clone https://github.com/davidharrishmc/riscv-wally cd riscv-wally +cd tests cd imperas-riscv-tests make -cd ../addins +cd ../../addins git clone https://github.com/riscv-non-isa/riscv-arch-test git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim @@ -32,6 +33,8 @@ edit Makefile.include make make XLEN=32 exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim +cd ../../wally-pipelined/linux-testgen/linux-testvectors +./tvLinker.sh ``` Notes: From 11efaa26694a9857dce6738019278b116b586004 Mon Sep 17 00:00:00 2001 From: Kevin Date: Wed, 3 Nov 2021 10:49:34 -0700 Subject: [PATCH 05/21] changed code aligner to run recursively on a root directory -only runs the aligner on .sv files -runs recursively on sub-directories --- wally-pipelined/src/ifu/CodeAligner.py | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/ifu/CodeAligner.py b/wally-pipelined/src/ifu/CodeAligner.py index 59f9de4e..579fd623 100644 --- a/wally-pipelined/src/ifu/CodeAligner.py +++ b/wally-pipelined/src/ifu/CodeAligner.py @@ -87,12 +87,26 @@ def Mod_Space_at(Ln,loc,diff): return NewString -def main_filehandler(overwrite=False): +'''def main_filehandler(overwrite=False): for filename in os.listdir(): - if ".py" not in filename: + if ".sv" in filename: GiantString = read_input(filename) SOV = ID_start(GiantString) ModifiedGS = modified_logNew(GiantString,SOV) - Newname = write_to_output(filename,ModifiedGS,overwrite) + Newname = write_to_output(filename,ModifiedGS,overwrite)''' +def root_filehandler(path,overwrite=False): + for f in os.listdir(path): + if os.path.isdir(f): + root_filehandler(path+"/"+f) + else: + if ".sv" in f: + GiantString = read_input(f) + SOV = ID_start(GiantString) + ModifiedGS = modified_logNew(GiantString,SOV) + Newname = write_to_output(f,ModifiedGS,overwrite) + + +def driver(overwrite=False): + root_filehandler(os.getcwd()) -main_filehandler(True) \ No newline at end of file +driver(True) \ No newline at end of file From 3f6b91845881b794d744763e5864460c49f6dc36 Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 3 Nov 2021 13:30:21 -0700 Subject: [PATCH 06/21] added wally-riscv-arch-test compile commands --- README.md | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 36fbbb4f..2de55cbc 100644 --- a/README.md +++ b/README.md @@ -8,10 +8,8 @@ To use Wally on Linux: ``` git clone https://github.com/davidharrishmc/riscv-wally cd riscv-wally -cd tests -cd imperas-riscv-tests -make -cd ../../addins +cd addins +*** can these clones be replaced with git submodule commands? git clone https://github.com/riscv-non-isa/riscv-arch-test git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim @@ -33,6 +31,13 @@ edit Makefile.include make make XLEN=32 exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim +cd ../../tests +cd imperas-riscv-tests +make +cd ../wally-riscv-arch-test +make +make XLEN=32 +exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim cd ../../wally-pipelined/linux-testgen/linux-testvectors ./tvLinker.sh ``` From 5b2816d3a59a69a0586fba7df39af2fb679b7a1a Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 3 Nov 2021 13:40:23 -0700 Subject: [PATCH 07/21] fixed 64i --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 2de55cbc..740f985f 100644 --- a/README.md +++ b/README.md @@ -15,7 +15,7 @@ git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F -cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv64i_m/D +cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D mkdir build cd build From 331e0f9f6ee882c673894a89248f96a493e09e2a Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 3 Nov 2021 13:49:07 -0700 Subject: [PATCH 08/21] fixed 64i --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 740f985f..db481872 100644 --- a/README.md +++ b/README.md @@ -13,6 +13,7 @@ cd addins git clone https://github.com/riscv-non-isa/riscv-arch-test git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim +*** replace these with a copy from ../install/F and ../install/D containing the Makefile.includes already updated cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D From 17e776f8535439b257373e3aadbed271ef932204 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 5 Nov 2021 22:37:05 -0700 Subject: [PATCH 10/21] checkpoints now use binary ram files --- .../testvector-generation/Makefile | 13 +++++++ .../testvector-generation/fixBinMem | Bin 0 -> 8784 bytes .../testvector-generation/fixBinMem.c | 33 ++++++++++++++++++ .../{fix_mem.py => fixTxtMem.py} | 0 .../testvector-generation/genCheckpoint.gdb | 7 ++-- .../testvector-generation/genCheckpoint.sh | 23 ++++++++---- .../testvector-generation/genInitMem.sh | 4 +-- .../testvector-generation/genSettings.sh | 2 +- wally-pipelined/testbench/testbench-linux.sv | 9 +++-- 9 files changed, 75 insertions(+), 16 deletions(-) create mode 100644 tests/linux-testgen/testvector-generation/Makefile create mode 100755 tests/linux-testgen/testvector-generation/fixBinMem create mode 100644 tests/linux-testgen/testvector-generation/fixBinMem.c rename tests/linux-testgen/testvector-generation/{fix_mem.py => fixTxtMem.py} (100%) diff --git a/tests/linux-testgen/testvector-generation/Makefile b/tests/linux-testgen/testvector-generation/Makefile new file mode 100644 index 00000000..8f9bff4b --- /dev/null +++ b/tests/linux-testgen/testvector-generation/Makefile @@ -0,0 +1,13 @@ +SHELL = /bin/sh + +CFLAG = -Wall -g +CC = clang + +all: fixBinMem + +fixBinMem: fixBinMem.c + ${CC} ${CFLAGS} fixBinMem.c -o fixBinMem + chmod +x fixBinMem + +clean: + -rm -f fixBinMem diff --git a/tests/linux-testgen/testvector-generation/fixBinMem b/tests/linux-testgen/testvector-generation/fixBinMem new file mode 100755 index 0000000000000000000000000000000000000000..563ed988d78611241ac015f656c16c9483981703 GIT binary patch literal 8784 zcmeHMZ){W76~DI09|AZI&=O!YuN|oZQ;ZWr6ev(TiNj0hK$bsr(-vNw_&IUs*p~g= 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zT4Q|}KGD$~-1QY-4v0ir?A~SN4wwafMR5nyisGx5=BL@117_644a#7rf;|t|!_cKsj_p8|7@MvF+7p4*m*(NvDQ1jg8Zw1O9h_j%ntysvb$K$ zvVJcj4xZAwUL|yY1vvHtUQ=M=F$2&)z~h4XHfU*ALderSGwNWP103b8{qTDsKPk>7 zJZ1s;>m28*1+R}+z#puDSHZwl**7oUW0A30F28*L+=lYS?(K$?T1rcY!|q|Ye|xU2 zM+tQH_9+U3i#v5BlG4nZ}Oi!@k_*f#ULQv{% z-o0l}aUlghbP*+(Oa_lD5VIza!);)2OjRIY9Xk#xCQboKtxz;F(He<$sbk#9jvil^ zU-2Jq2QPJ(DPN!%VoLir4*R+~+d#@x!Y>>Fg73cKmlfTb+}^{KLxCf$zJPM1qodc~ zr}X(+1AeT5UsDdJ(!2@!C8pPFzMNFlP*4k!q;a8Xky21fzulxuP^(12{U>yGDz1zM zW1*Q7GjFh*VQI^SHHe3 zENAZ2@i8qp1XN4vbd+*%ud5~#%njEJs@vDvSr11Z!HvYy?xA!9?%yLJ=0Om7 z(D4}9)2Wu!OT@XUfKi|Qk)BZ98)PgX8$<|FFdcH zDCyHV*(3BRKBM}r?SDn+w*tjP@!p`&r}z-{vCpjfuK|XBp?{d@+`TCDDel!vm(QOJ z6qxnteC`qsCrD9HmxX@MqEF}eNuf{vk{K)iLyJCrpU(^Zo~6K9w?Oriy&qfjDK5Ar zDx$cUgCS zi@vq~Yfz4V6;n6S`I7!$waODu^aIeXH0e`(Q;kL;k(|yMJmG(a0-QfoKgB`Pf6ym; ze}N3nUDBs`iT?kdN8^xaep9_P4=zBNxqgbPa@Z(HB(HM@PxvQLVAfxXzeEKxDGEw@ zL~|B>ItR-_-#Xq_{vqh2Eowjh;e;t5^r@X3gcsFIyaSv^|2+f +#include +#include +int main(int argc, char *argv[]) { + if (argc < 3){ + fprintf(stderr, "Expected 2 arguments: \n"); + exit(1); + } + char* rawGDBfilePath = argv[1]; + FILE* rawGDBfile; + if ((rawGDBfile = fopen(rawGDBfilePath,"rb"))==NULL) { + fprintf(stderr, "File not found: %s\n",rawGDBfilePath); + exit(1); + } + char* outFilePath = argv[2]; + FILE* outFile = fopen(outFilePath,"w"); + uint64_t qemuWord; + uint64_t verilogWord; + int bytesReturned=0; + do { + bytesReturned=fread(&qemuWord, 8, 1, rawGDBfile); + verilogWord = (((qemuWord>>0 )&0xff)<<56 | + ((qemuWord>>8 )&0xff)<<48 | + ((qemuWord>>16)&0xff)<<40 | + ((qemuWord>>24)&0xff)<<32 | + ((qemuWord>>32)&0xff)<<24 | + ((qemuWord>>40)&0xff)<<16 | + ((qemuWord>>48)&0xff)<<8 | + ((qemuWord>>56)&0xff)<<0); + fwrite(&verilogWord, 8, 1, outFile); + } while(bytesReturned!=0); + return 0; +} diff --git a/tests/linux-testgen/testvector-generation/fix_mem.py b/tests/linux-testgen/testvector-generation/fixTxtMem.py similarity index 100% rename from tests/linux-testgen/testvector-generation/fix_mem.py rename to tests/linux-testgen/testvector-generation/fixTxtMem.py diff --git a/tests/linux-testgen/testvector-generation/genCheckpoint.gdb b/tests/linux-testgen/testvector-generation/genCheckpoint.gdb index 92630698..a7744139 100755 --- a/tests/linux-testgen/testvector-generation/genCheckpoint.gdb +++ b/tests/linux-testgen/testvector-generation/genCheckpoint.gdb @@ -13,7 +13,7 @@ define genCheckpoint set $checkPC=$arg3 set $checkPCoccurences=$arg4 eval "set $statePath = \"%s/stateGDB.txt\"", $statePath - eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath + eval "set $ramPath = \"%s/ramGDB.bin\"", $ramPath # Connect to QEMU session eval "target extended-remote :%d",$tcpPort @@ -46,10 +46,7 @@ define genCheckpoint # Log main memory to a file printf "GDB storing RAM to %s\n", $ramPath - eval "set logging file %s", $ramPath - set logging on - x/134217728xb 0x80000000 - set logging off + eval "dump binary memory %s 0x80000000 0xffffffff", $ramPath kill q diff --git a/tests/linux-testgen/testvector-generation/genCheckpoint.sh b/tests/linux-testgen/testvector-generation/genCheckpoint.sh index cca7486e..ca4bcf49 100755 --- a/tests/linux-testgen/testvector-generation/genCheckpoint.sh +++ b/tests/linux-testgen/testvector-generation/genCheckpoint.sh @@ -3,7 +3,7 @@ source genSettings.sh tcpPort=1236 -instrs=450000000 +instrs=8500000 checkOutDir="$outDir/checkpoint$instrs" checkIntermedDir="$checkOutDir/intermediate-outputs" @@ -15,24 +15,35 @@ if [[ $REPLY =~ ^[Yy]$ ]] then mkdir -p $checkOutDir mkdir -p $checkIntermedDir + + # Identify instruction in trace instr=$(sed "${instrs}q;d" "../linux-testvectors/all.txt") - echo "Found ${instrs}th instr: ${instr}." + echo "Found ${instrs}th instr: ${instr}" pc=$(echo $instr | cut -d " " -f1) asm=$(echo $instr | cut -d " " -f2) occurences=$(($(head -$instrs "../linux-testvectors/all.txt" | grep -c "${pc} ${asm}")-1)) echo "It occurs ${occurences} times before the ${instrs}th instr." - # Simulate QEMU, parse QEMU trace, run GDB script which logs a bunch of data at the checkpoint + + # GDB+QEMU + echo "Starting QEMU with attached GDB script at $(date +%H:%M:%S)" ($customQemu \ -M virt \ -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on,rr=replay,rrfile="$intermedDir/$recordFile" \ -gdb tcp::$tcpPort -S) \ - & riscv64-unknown-elf-gdb -x genCheckpoint.gdb -ex "genCheckpoint $tcpPort $instrs \"$checkIntermedDir\" \"$pc\" $occurences" + & riscv64-unknown-elf-gdb --quiet \ + -x genCheckpoint.gdb -ex "genCheckpoint $tcpPort $instrs \"$checkIntermedDir\" \"$pc\" $occurences" + echo "Completed GDB script completed at $(date +%H:%M:%S)" + # Post-Process GDB outputs ./parseState.py "$checkOutDir" - ./fix_mem.py "$checkIntermedDir/ramGDB.txt" "$checkOutDir/ram.txt" - tail -n+$(($instrs+1)) "$outDir/$traceFile" > "$checkOutDir/$traceFile" + echo "Changing Endianness at $(date +%H:%M:%S)" + make + ./fixBinMem "$checkIntermedDir/ramGDB.bin" "$checkOutDir/ram.bin" + echo "Creating truncated trace at $(date +%H:%M:%S)" + tail -n+$instrs "$outDir/$traceFile" > "$checkOutDir/$traceFile" + echo "Checkpoint completed at $(date +%H:%M:%S)" else echo "You can change the number of instructions by editing the \"instrs\" variable in this script." echo "Have a nice day!" diff --git a/tests/linux-testgen/testvector-generation/genInitMem.sh b/tests/linux-testgen/testvector-generation/genInitMem.sh index 56b30a45..f82556f5 100755 --- a/tests/linux-testgen/testvector-generation/genInitMem.sh +++ b/tests/linux-testgen/testvector-generation/genInitMem.sh @@ -16,8 +16,8 @@ then & riscv64-unknown-elf-gdb -quiet -x genInitMem.gdb -ex "genInitMem $tcpPort \"$intermedDir\"" echo "Translating Mem from GDB to Questa format" - ./fix_mem.py "$intermedDir/bootmemGDB.txt" "$outDir/bootmem.txt" - ./fix_mem.py "$intermedDir/ramGDB.txt" "$outDir/ram.txt" + ./fixTxtMem.py "$intermedDir/bootmemGDB.txt" "$outDir/bootmem.txt" + ./fixTxtMem.py "$intermedDir/ramGDB.txt" "$outDir/ram.txt" echo "Done" echo "Creating debugging objdump of linux image" diff --git a/tests/linux-testgen/testvector-generation/genSettings.sh b/tests/linux-testgen/testvector-generation/genSettings.sh index 57bd7765..59490e35 100755 --- a/tests/linux-testgen/testvector-generation/genSettings.sh +++ b/tests/linux-testgen/testvector-generation/genSettings.sh @@ -4,7 +4,7 @@ # *** on the long term we'll want to include QEMU in the addins folder export customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64" export imageDir="../buildroot-image-output" -export outDir="../linux-testvectors-experimental" +export outDir="../linux-testvectors" export intermedDir="$outDir/intermediate-outputs" export traceFile="all.txt" export recordFile="all.qemu" diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 72adf589..68bf64ad 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -280,7 +280,9 @@ module testbench(); `INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]); `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0); - assign initPriv = (initPC[0][`XLEN-1]) ? 2'h2 : 2'h3; // *** a hacky way to detect initial privilege level + integer ramFile; + integer readResult; + assign initPriv = (initPC[0][`XLEN-1]) ? 2'h1 : 2'h3; // *** a hacky way to detect initial privilege level initial begin force dut.hart.priv.SwIntM = 0; force dut.hart.priv.TimerIntM = 0; @@ -297,7 +299,10 @@ module testbench(); end else begin // checkpoint $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT); checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir}; - $readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM); + //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM); + ramFile = $fopen({checkpointDir,"ram.bin"}, "rb"); + readResult = $fread(dut.uncore.dtim.RAM,ramFile); + $fclose(ramFile); data_file_all = $fopen({checkpointDir,"all.txt"}, "r"); InstrCountW = CHECKPOINT; // manual checkpoint initializations that don't neatly fit into MACRO From c92d41a597476359d84a5f6ee0bc708928b8a649 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 6 Nov 2021 03:44:23 -0700 Subject: [PATCH 11/21] checkpoint MIDELEG support --- wally-pipelined/testbench/testbench-linux.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index e6896aff..249cf390 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -275,6 +275,7 @@ module testbench(); endgenerate `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); + `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIE, [11:0]); `INIT_CHECKPOINT_VAL(MIP, [11:0]); `INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]); From 8c926dcfd24063cb81cdb368d2098cd23498aa85 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 6 Nov 2021 14:14:15 -0700 Subject: [PATCH 12/21] make genCheckpoint accept instr count as argument --- .../testvector-generation/genCheckpoint.sh | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/tests/linux-testgen/testvector-generation/genCheckpoint.sh b/tests/linux-testgen/testvector-generation/genCheckpoint.sh index ca4bcf49..7671d752 100755 --- a/tests/linux-testgen/testvector-generation/genCheckpoint.sh +++ b/tests/linux-testgen/testvector-generation/genCheckpoint.sh @@ -2,11 +2,20 @@ source genSettings.sh tcpPort=1236 - -instrs=8500000 checkOutDir="$outDir/checkpoint$instrs" checkIntermedDir="$checkOutDir/intermediate-outputs" +# Parse Commandline Arg +if [ "$#" -ne 1 ]; then + echo "genCheckpoint requires 1 argument: " >&2 + exit 1 +fi +instrs=$1 +if ! [ "$instrs" -eq "$instrs" ] 2> /dev/null +then + echo "Error expected integer number of instructions, got $instrs" >&2 + exit 1 +fi read -p "This scripts is going to create a checkpoint at $instrs instrs. Is that what you wanted? (y/n) " -n 1 -r From 97403af40307e6ba1b7f2a234ae3f6dc82aac4c1 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 6 Nov 2021 14:15:16 -0700 Subject: [PATCH 13/21] update tvLinker to new shared dir --- tests/linux-testgen/linux-testvectors/tvLinker.sh | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tests/linux-testgen/linux-testvectors/tvLinker.sh b/tests/linux-testgen/linux-testvectors/tvLinker.sh index f1004919..ff7dc3e5 100755 --- a/tests/linux-testgen/linux-testvectors/tvLinker.sh +++ b/tests/linux-testgen/linux-testvectors/tvLinker.sh @@ -1,9 +1,3 @@ echo "Warning: this script will only work if your repo is on Tera" -ln -s /courses/e190ax/buildroot_boot/all.txt all.txt -ln -s /courses/e190ax/buildroot_boot/bootmem.txt bootmem.txt -ln -s /courses/e190ax/buildroot_boot/ram.txt ram.txt -ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump vmlinux.objdump -ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.addr vmlinux.objdump.addr -ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.lab vmlinux.objdump.lab -ln -s /courses/e190ax/buildroot_boot/checkpoint8500000 ./checkpoint8500000 +ln -s /courses/e190ax/linux-testvectors-shared/* ./ echo "Done!" From 9f2a58359058020c3429fed70f2921be0f212d2e Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 6 Nov 2021 14:37:49 -0700 Subject: [PATCH 14/21] automated checkpoint generator --- tests/linux-testgen/testvector-generation/checkpointSweep.sh | 5 +++++ tests/linux-testgen/testvector-generation/genCheckpoint.sh | 1 + 2 files changed, 6 insertions(+) create mode 100755 tests/linux-testgen/testvector-generation/checkpointSweep.sh diff --git a/tests/linux-testgen/testvector-generation/checkpointSweep.sh b/tests/linux-testgen/testvector-generation/checkpointSweep.sh new file mode 100755 index 00000000..bc04bbf7 --- /dev/null +++ b/tests/linux-testgen/testvector-generation/checkpointSweep.sh @@ -0,0 +1,5 @@ +for index in {0..105} +do + instrs=$(((400+$index)*1000000)) + echo "y" | ./genCheckpoint.sh $instrs +done diff --git a/tests/linux-testgen/testvector-generation/genCheckpoint.sh b/tests/linux-testgen/testvector-generation/genCheckpoint.sh index 7671d752..97cdf8a0 100755 --- a/tests/linux-testgen/testvector-generation/genCheckpoint.sh +++ b/tests/linux-testgen/testvector-generation/genCheckpoint.sh @@ -22,6 +22,7 @@ Is that what you wanted? (y/n) " -n 1 -r echo if [[ $REPLY =~ ^[Yy]$ ]] then + echo "Creating checkpoint at $instrs instructions!" mkdir -p $checkOutDir mkdir -p $checkIntermedDir From f6a555009b02808b1a859752fd378809b2f655a2 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 6 Nov 2021 14:57:29 -0700 Subject: [PATCH 15/21] increase expectations for buildroot and timeout count --- wally-pipelined/regression/regression-wally.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index ada9fe38..d1008532 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -32,7 +32,7 @@ configs = [ ] def getBuildrootTC(short): INSTR_LIMIT = 100000 # multiple of 100000 - MAX_EXPECTED = 3000000 + MAX_EXPECTED = 14000000 if short: BRcmd="vsim > {} -c < Date: Sat, 6 Nov 2021 15:02:16 -0700 Subject: [PATCH 16/21] update README.md to reflect new tvLinker location --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index db481872..b97a5efd 100644 --- a/README.md +++ b/README.md @@ -39,7 +39,7 @@ cd ../wally-riscv-arch-test make make XLEN=32 exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim -cd ../../wally-pipelined/linux-testgen/linux-testvectors +cd ../../tests/linux-testgen/linux-testvectors ./tvLinker.sh ``` From e4da37934004cbfe9923b4206130d44311670b17 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 6 Nov 2021 15:25:10 -0700 Subject: [PATCH 17/21] genCheckpoint path bugfix --- tests/linux-testgen/testvector-generation/genCheckpoint.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/linux-testgen/testvector-generation/genCheckpoint.sh b/tests/linux-testgen/testvector-generation/genCheckpoint.sh index 97cdf8a0..85102f87 100755 --- a/tests/linux-testgen/testvector-generation/genCheckpoint.sh +++ b/tests/linux-testgen/testvector-generation/genCheckpoint.sh @@ -2,8 +2,6 @@ source genSettings.sh tcpPort=1236 -checkOutDir="$outDir/checkpoint$instrs" -checkIntermedDir="$checkOutDir/intermediate-outputs" # Parse Commandline Arg if [ "$#" -ne 1 ]; then @@ -16,6 +14,8 @@ then echo "Error expected integer number of instructions, got $instrs" >&2 exit 1 fi +checkOutDir="$outDir/checkpoint$instrs" +checkIntermedDir="$checkOutDir/intermediate-outputs" read -p "This scripts is going to create a checkpoint at $instrs instrs. Is that what you wanted? (y/n) " -n 1 -r From 7cb8b76ef639bf5babe05c2f7d24f6bc06c702ac Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 9 Nov 2021 10:55:48 -0800 Subject: [PATCH 18/21] Makefile added in regression directory: -cd's into imperas then runs make commands, finally running the tvLinker script --- wally-pipelined/regression/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 wally-pipelined/regression/Makefile diff --git a/wally-pipelined/regression/Makefile b/wally-pipelined/regression/Makefile new file mode 100644 index 00000000..cdebb5c0 --- /dev/null +++ b/wally-pipelined/regression/Makefile @@ -0,0 +1,6 @@ +make all: + make ../../tests/imperas-riscv-tests/ + make ../../tests/wally-riscv-arch-test/ + make XLEN=32 ../../tests/wally-riscv-arch-test/ + exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf + cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh From 3dd83b3113e85711665d4035d5614f511033b3c7 Mon Sep 17 00:00:00 2001 From: Skylar Litz Date: Thu, 11 Nov 2021 09:35:51 -0800 Subject: [PATCH 20/21] fix timing of delayed interrupt --- wally-pipelined/testbench/testbench-linux.sv | 24 ++++++++++++-------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 249cf390..2ca31e58 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -470,8 +470,12 @@ module testbench(); if(CheckMIPFutureE) CheckMIPFutureE <= 0; CheckMIPFutureM <= CheckMIPFutureE; if(CheckMIPFutureM) begin - if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin - RequestDelayedMIP = 1; + $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); + $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); + $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); + if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 16)) begin + // if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin + RequestDelayedMIP <= 1; $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); end else begin // update MIP immediately $display("%tns: Updating MIP to %x",$time,NextMIPexpected); @@ -488,14 +492,14 @@ module testbench(); $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]); $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]); - if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin - RequestDelayedMIP = 1; - $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); - end else begin - $display("%tns: Updating MIP to %x",$time,NextMIPexpected); - MIPexpected = NextMIPexpected; - force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; - end + // if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin + // RequestDelayedMIP = 1; + // $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); + // end else begin + // $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + // MIPexpected = NextMIPexpected; + // force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; + // end end if(RequestDelayedMIP) begin $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); From 2203590f9fe70d09b97e314edce83da3c169529a Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 15 Nov 2021 14:49:00 -0800 Subject: [PATCH 21/21] get current privilege level from GDB for checkpoints --- tests/linux-testgen/testvector-generation/parseState.py | 5 +++-- wally-pipelined/testbench/testbench-linux.sv | 6 ++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/tests/linux-testgen/testvector-generation/parseState.py b/tests/linux-testgen/testvector-generation/parseState.py index 9a2173b0..bbbf535b 100755 --- a/tests/linux-testgen/testvector-generation/parseState.py +++ b/tests/linux-testgen/testvector-generation/parseState.py @@ -34,7 +34,8 @@ stateGDBpath = outDir+'intermediate-outputs/stateGDB.txt' if not os.path.exists(stateGDBpath): sys.exit('Error input file '+stateGDBpath+'not found') -singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus'] +singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv'] +# priv (current privilege mode) isn't technically a CSR but we can log it with the same machinery thirtyTwoBitCSRs = ['mcounteren','scounteren'] listCSRs = ['hpmcounter','pmpaddr'] pmpcfg = ['pmpcfg'] @@ -75,7 +76,7 @@ with open(stateGDBpath, 'r') as stateGDB: outFile = open(outDir+outFileName, 'w') outFile.write(val+'\n') outFile.close() - if name in thirtyTwoBitCSRs: + elif name in thirtyTwoBitCSRs: outFileName = 'checkpoint-'+name.upper() outFile = open(outDir+outFileName, 'w') val = int(val,16) & 0xffffffff diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 2ca31e58..eb820c13 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -197,7 +197,7 @@ module testbench(); `define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE `define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE `define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE - `define CURR_PRIV dut.hart.priv.privmodereg.q + `define PRIV dut.hart.priv.privmodereg.q `define INSTRET dut.hart.priv.csr.genblk1.counters.genblk1.genblk2.INSTRETreg.q // Common Macros `define checkCSR(CSR) \ @@ -289,11 +289,11 @@ module testbench(); `INIT_CHECKPOINT_VAL(MTVEC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(STVEC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]); + `INIT_CHECKPOINT_VAL(PRIV, [1:0]); `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0); integer ramFile; integer readResult; - assign initPriv = (initPC[0][`XLEN-1]) ? 2'h1 : 2'h3; // *** a hacky way to detect initial privilege level initial begin force dut.hart.priv.SwIntM = 0; force dut.hart.priv.TimerIntM = 0; @@ -325,7 +325,6 @@ module testbench(); force {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE} = initMSTATUS[0][5:3]; force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0]; force `INSTRET = CHECKPOINT; - force `CURR_PRIV = initPriv; while (reset!==1) #1; while (reset!==0) #1; #1; @@ -335,7 +334,6 @@ module testbench(); release {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE}; release {`STATUS_SIE,`STATUS_UIE}; release `INSTRET; - release `CURR_PRIV; end // Get the E-stage trace reader ahead of the M-stage trace reader matchCountE = $fgets(lineE,traceFileE);