From c5dfefe6690583f32f2843d2c382bb5fcd761851 Mon Sep 17 00:00:00 2001 From: James Stine Date: Fri, 8 Jul 2022 08:09:55 -0500 Subject: [PATCH] Update SRAM to /proj/wally --- pipelined/src/cache/sram1p1rw.sv | 6 +++--- .../src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 134a14b0..1b853702 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -57,9 +57,9 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = ByteMask[index/8]; TS1N28HPCPSVTB64X128M4SWBASO sram( - .SLP(1'b0), .SD(1'b0), .CLK(clk), .CEB(1'b0), .WEB(~WriteEnable), - .CEBM(1'b0), .WEBM(1'b0), .AWT(1'b0), .A(Adr), .D(CacheWriteData), - .BWEB(~BitWriteMask), .AM('b0), .DM('b0), .BWEBM('b0), .BIST(1'b0), .Q(ReadData) + .CLK(clk), .CEB(1'b0), .WEB(~WriteEnable), + .A(Adr), .D(CacheWriteData), + .BWEB(~BitWriteMask), .Q(ReadData) ); end else begin diff --git a/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v b/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v index 71972067..c8197520 120000 --- a/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v +++ b/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v @@ -1 +1 @@ -/home/jstine/memory/ts1n28hpcpsvtb64x128m4swbaso_180a/VERILOG/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v \ No newline at end of file +/proj/wally/memory/ts1n28hpcpsvtb64x128m4sw_180a/VERILOG/ts1n28hpcpsvtb64x128m4sw_180a_tt1v25c.v \ No newline at end of file