From c54d81ab0449c4588fcb8de513634bf98bce7138 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 30 Dec 2021 03:01:21 +0000
Subject: [PATCH] Fixed generate statement name in csrm for buildroot
 regression

---
 wally-pipelined/src/privileged/csrm.sv       | 17 +++++------------
 wally-pipelined/testbench/testbench-linux.sv |  8 ++++----
 2 files changed, 9 insertions(+), 16 deletions(-)

diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv
index 2d6ff19d..f77310ca 100644
--- a/wally-pipelined/src/privileged/csrm.sv
+++ b/wally-pipelined/src/privileged/csrm.sv
@@ -144,7 +144,7 @@ module csrm #(parameter
   // CSRs
   flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); //busybear: changed reset value to 0
   generate
-    if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist
+    if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin:deleg // DELEG registers should exist
       flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW);
       flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW);
     end else begin
@@ -158,13 +158,12 @@ module csrm #(parameter
   flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
   if(`QEMU) assign MTVAL_REGW = `XLEN'b0;
   else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
-  generate
-    if (`BUSYBEAR == 1)
+  generate // *** needs comment about bit 1
+    if (`BUSYBEAR == 1) begin:counters
       flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, MCOUNTEREN_REGW);
-    else if (`BUILDROOT == 1)
+    end else  begin:counters
       flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
-    else
-      flopens #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
+    end
   endgenerate
   flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
 
@@ -187,10 +186,6 @@ module csrm #(parameter
         entry = (CSRAdrM - PMPCFG0)*4;
         CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
       end
-
-      /*
-      if (~CSRAdrM[0]) CSRMReadValM = {PMPCFG_ARRAY_REGW[]};
-      else             CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG_ARRAY_REGW[(CSRAdrM - PMPCFG0-1)/2][63:32]};*/
     end
     else case (CSRAdrM) 
       MISA_ADR:  CSRMReadValM = MISA_REGW;
@@ -201,8 +196,6 @@ module csrm #(parameter
       MSTATUS:   CSRMReadValM = MSTATUS_REGW;
       MSTATUSH:  CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported
       MTVEC:     CSRMReadValM = MTVEC_REGW;
-      //MEDELEG:   CSRMReadValM = {{(`XLEN-12){1'b0}}, MEDELEG_REGW};
-      //MIDELEG:   CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW};
       MEDELEG:   CSRMReadValM = MEDELEG_REGW;
       MIDELEG:   CSRMReadValM = MIDELEG_REGW;
       MIP:       CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW};
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index 915ceee8..2444a343 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -175,18 +175,18 @@ module testbench();
   `define PC          dut.hart.ifu.pcreg.q
   `define CSR_BASE    dut.hart.priv.priv.csr
   `define HPMCOUNTER  `CSR_BASE.counters.genblk1.HPMCOUNTER_REGW
-  `define PMP_BASE    `CSR_BASE.csrm.genblk4
+  `define PMP_BASE    `CSR_BASE.csrm.pmp
   `define PMPCFG      genblk2.PMPCFGreg.q
   `define PMPADDR     PMPADDRreg.q
-  `define MEDELEG     `CSR_BASE.csrm.genblk1.MEDELEGreg.q
-  `define MIDELEG     `CSR_BASE.csrm.genblk1.MIDELEGreg.q
+  `define MEDELEG     `CSR_BASE.csrm.deleg.MEDELEGreg.q
+  `define MIDELEG     `CSR_BASE.csrm.deleg.MIDELEGreg.q
   `define MIE         `CSR_BASE.csri.MIE_REGW
   `define MIP         `CSR_BASE.csri.MIP_REGW
   `define MCAUSE      `CSR_BASE.csrm.MCAUSEreg.q
   `define SCAUSE      `CSR_BASE.csrs.genblk1.SCAUSEreg.q
   `define MEPC        `CSR_BASE.csrm.MEPCreg.q
   `define SEPC        `CSR_BASE.csrs.genblk1.SEPCreg.q
-  `define MCOUNTEREN  `CSR_BASE.csrm.genblk3.MCOUNTERENreg.q
+  `define MCOUNTEREN  `CSR_BASE.csrm.counters.MCOUNTERENreg.q
   `define SCOUNTEREN  `CSR_BASE.csrs.genblk1.genblk2.SCOUNTERENreg.q
   `define MSCRATCH    `CSR_BASE.csrm.MSCRATCHreg.q
   `define SSCRATCH    `CSR_BASE.csrs.genblk1.SSCRATCHreg.q