diff --git a/wally-pipelined/lint-wally b/wally-pipelined/lint-wally
index ed67dbab..47a43235 100755
--- a/wally-pipelined/lint-wally
+++ b/wally-pipelined/lint-wally
@@ -1,11 +1,12 @@
 #!/bin/bash
 # check for warnings in Verilog code
 # The verilator lint tool is faster and better than Modelsim so it is best to run this first.
+verilator="/usr/local/bin/verilator"
 
 basepath=$(dirname $0)
 for config in rv64ic rv32ic; do
     echo "$config linting..."
-    if !(verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/$config" $basepath/src/*/*.sv); then
+    if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/$config" $basepath/src/*/*.sv); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi