From e74d47bcb48ece617be64548ee277e578fa72997 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 08:36:45 -0800 Subject: [PATCH 1/2] Renamed renamed sram to ram --- pipelined/src/cache/cacheway.sv | 4 ++-- pipelined/src/generic/mem/{sram1p1rw.sv => ram1p1rwbe.sv} | 2 +- pipelined/src/generic/mem/{sram2p1r1w.sv => ram2p1r1wb.sv} | 4 ++-- pipelined/src/ifu/BTBPredictor.sv | 4 ++-- pipelined/src/ifu/globalHistoryPredictor.sv | 2 +- pipelined/src/ifu/gsharePredictor.sv | 2 +- pipelined/src/ifu/localHistoryPredictor.sv | 4 ++-- pipelined/src/ifu/twoBitPredictor.sv | 2 +- pipelined/src/lsu/dtim.sv | 2 +- pipelined/src/uncore/ram_ahb.sv | 2 +- 10 files changed, 14 insertions(+), 14 deletions(-) rename pipelined/src/generic/mem/{sram1p1rw.sv => ram1p1rwbe.sv} (98%) rename pipelined/src/generic/mem/{sram2p1r1w.sv => ram2p1r1wb.sv} (98%) diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 5f986954..0639fcf9 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -116,7 +116,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// - sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), + ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), .addr(CAdr), .dout(ReadTag), .bwe('1), .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); @@ -139,7 +139,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, localparam integer LOGNUMSRAM = $clog2(NUMSRAM); for(words = 0; words < NUMSRAM; words++) begin: word - sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr), + ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); diff --git a/pipelined/src/generic/mem/sram1p1rw.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv similarity index 98% rename from pipelined/src/generic/mem/sram1p1rw.sv rename to pipelined/src/generic/mem/ram1p1rwbe.sv index 45668125..0a7f7424 100644 --- a/pipelined/src/generic/mem/sram1p1rw.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -35,7 +35,7 @@ `include "wally-config.vh" -module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( +module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, diff --git a/pipelined/src/generic/mem/sram2p1r1w.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv similarity index 98% rename from pipelined/src/generic/mem/sram2p1r1w.sv rename to pipelined/src/generic/mem/ram2p1r1wb.sv index d18a9619..ff3257eb 100644 --- a/pipelined/src/generic/mem/sram2p1r1w.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// sram2p1r1w +// ram2p1r1wb // // Written: Ross Thomposn // Email: ross1728@gmail.com @@ -40,7 +40,7 @@ `include "wally-config.vh" -module sram2p1r1w +module ram2p1r1wb #(parameter int DEPTH = 10, parameter int WIDTH = 2 ) diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv index a07efcdf..f03bbdd5 100644 --- a/pipelined/src/ifu/BTBPredictor.sv +++ b/pipelined/src/ifu/BTBPredictor.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// sram2p1r1w +// ram2p1r1wb // // Written: Ross Thomposn // Email: ross1728@gmail.com @@ -103,7 +103,7 @@ module BTBPredictor // *** need to add forwarding. // *** optimize for byte write enables - sram2p1r1w #(Depth, `XLEN+5) memory(.clk(clk), + ram2p1r1wb #(Depth, `XLEN+5) memory(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1({{InstrClass, TargetPC}}), diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv index f40eb172..6d06dc8c 100644 --- a/pipelined/src/ifu/globalHistoryPredictor.sv +++ b/pipelined/src/ifu/globalHistoryPredictor.sv @@ -113,7 +113,7 @@ module globalHistoryPredictor assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - sram2p1r1w #(k, 2) PHT(.clk(clk), + ram2p1r1wb #(k, 2) PHT(.clk(clk), .reset(reset), //.RA1(GHR[k-1:0]), .RA1(GHRLookup), diff --git a/pipelined/src/ifu/gsharePredictor.sv b/pipelined/src/ifu/gsharePredictor.sv index 7a2b5627..ff111a3e 100644 --- a/pipelined/src/ifu/gsharePredictor.sv +++ b/pipelined/src/ifu/gsharePredictor.sv @@ -110,7 +110,7 @@ module gsharePredictor assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - sram2p1r1w #(`BPRED_SIZE, 2) PHT(.clk(clk), + ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk), .reset(reset), //.RA1(GHR[`BPRED_SIZE-1:0]), .RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 5826496a..97b2b6f5 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -60,7 +60,7 @@ module localHistoryPredictor assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]}; // INCASE we do ahead pipelining - // sram2p1r1w #(m,k) LHR(.clk(clk)), + // ram2p1r1wb #(m,k) LHR(.clk(clk)), // .reset(reset), // .RA1(LookUpPCIndex), // need hashing function to get correct PC address // .RD1(LHRF), @@ -84,7 +84,7 @@ module localHistoryPredictor // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT // LHR referes to the address that the past k branches points to in the prediction stage // LHRE refers to the address that the past k branches points to in the exectution stage - sram2p1r1w #(k, 2) PHT(.clk(clk), + ram2p1r1wb #(k, 2) PHT(.clk(clk), .reset(reset), .RA1(ForwardLHRNext), .RD1(PredictionMemory), diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv index 59827526..5ffb29d3 100644 --- a/pipelined/src/ifu/twoBitPredictor.sv +++ b/pipelined/src/ifu/twoBitPredictor.sv @@ -60,7 +60,7 @@ module twoBitPredictor assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]}; - sram2p1r1w #(Depth, 2) PHT(.clk(clk), + ram2p1r1wb #(Depth, 2) PHT(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1(PredictionMemory), diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 8f991883..9d83332f 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -46,7 +46,7 @@ module dtim( assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. - sram1p1rw #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) + ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); endmodule diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv index df87bb47..230b54c9 100644 --- a/pipelined/src/uncore/ram_ahb.sv +++ b/pipelined/src/uncore/ram_ahb.sv @@ -73,7 +73,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) ( mux2 #(`PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); // single-ported RAM - sram1p1rw #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1), + ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); From 03c700d91c67952b6f0f3ba5a3114ccd15c601f6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 10:56:33 -0800 Subject: [PATCH 2/2] Restored rv32d arch test after new push --- tests/riscof/spike/spike_rv32imc_isa.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml index f3caef84..04a5da18 100644 --- a/tests/riscof/spike/spike_rv32imc_isa.yaml +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -1,11 +1,11 @@ hart_ids: [0] hart0: - ISA: RV32IMAFCZicsr_Zifencei + ISA: RV32IMAFDCZicsr_Zifencei physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x40001125 + reset-val: 0x4000112D rv32: accessible: true mxl: