diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index ca82c4f8..8190b317 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -127,10 +127,10 @@ module fdivsqrtpostproc(
   
   always_comb
     if (RemOpM) begin
-      NormShiftM = (m + (`DIVBLEN)'(`DIVa));
+      NormShiftM = (m + (`DIVBLEN+1)'(`DIVa));
       PreResultM = IntRemM;
     end else begin
-      NormShiftM = ((`DIVBLEN)'(`DIVb) - (n << `LOGR));
+      NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (n << `LOGR));
       PreResultM = {3'b000, IntQuotM};
     end