From 6d2d7d181eabf6068ec0a16c91a69769d84bfa72 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 8 Mar 2023 17:11:27 -0600
Subject: [PATCH] Updated testbench to record coremark performance counters.
Added comment about mtval probably not being correct for compressed
instructions.
---
sim/wave.do | 9 ++++-----
src/privileged/csr.sv | 2 +-
testbench/testbench.sv | 11 +++++++++++
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/sim/wave.do b/sim/wave.do
index fd95f6f1..5aa5deb0 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -366,11 +366,9 @@ add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VI
add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
@@ -467,7 +465,6 @@ add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/d
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
-add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
@@ -635,8 +632,10 @@ add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMis
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/HPMCSample/InitialHPMCOUNTERH
+add wave -noupdate /testbench/HPMCSample/EndSample
+add wave -noupdate /testbench/HPMCSample/StartSample
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {49231900 ns} 0} {{Cursor 5} {394987 ns} 1}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {23 ns} 0} {{Cursor 5} {394987 ns} 1}
quietly wave cursor active 4
configure wave -namecolwidth 250
configure wave -valuecolwidth 194
@@ -652,4 +651,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {49231842 ns} {49231960 ns}
+WaveRestoreZoom {0 ns} {52 ns}
diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index d97be53f..0764e6c6 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -133,7 +133,7 @@ module csr #(parameter
if (InterruptM) NextFaultMtvalM = 0;
else case (CauseM)
12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint
- 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault
+ 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault // *** this should probably set to the uncompressed instruction
0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
default: NextFaultMtvalM = 0; // Ecall, interrupts
endcase
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index c4581fa8..b0af190a 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -447,6 +447,17 @@ logic [3:0] dummy;
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+ end else if(TEST == "coremark") begin
+ // embench runs warmup then runs start_trigger
+ // embench end with stop_trigger.
+ assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
+ flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+ assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+
+ assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
+ flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
+ assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+
end else begin
// default start condiction is reset
// default end condiction is end of test (DCacheFlushDone)