From c43b19120f5ae5089f809b12fe5782455e6588ea Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 25 Oct 2021 22:05:11 -0500
Subject: [PATCH] Fixed another critical path in the caches.

---
 wally-pipelined/src/cache/cacheway.sv | 33 +++++++++++++++++++++------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv
index 242d596f..9599ce46 100644
--- a/wally-pipelined/src/cache/cacheway.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -64,6 +64,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   logic [TAGLEN-1:0] 		      VicDirtyWay;
   logic [TAGLEN-1:0] 		      FlushThisWay;
 
+  logic [$clog2(NUMLINES)-1:0] 	      RAdrD, WAdrD;
+  logic 			      SetValidD, ClearValidD;
+  logic 			      SetDirtyD, ClearDirtyD;
+  logic 			      WriteEnableD, VDWriteEnableD;
+  
+  
+  
+
   genvar 			      words;
 
   generate
@@ -108,28 +116,39 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   	ValidBits <= {NUMLINES{1'b0}};
     else if (InvalidateAll) 
   	ValidBits <= {NUMLINES{1'b0}};
-    else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1;
-    else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0;
+    else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b1;
+    else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b0;
   end
 
   always_ff @(posedge clk) begin
-    Valid <= ValidBits[RAdr];
+    RAdrD <= RAdr;
+    WAdrD <= WAdr;
+    SetValidD <= SetValid;
+    ClearValidD <= ClearValid;    
+    WriteEnableD <= WriteEnable;
+    VDWriteEnableD <= VDWriteEnable;
   end
 
+    
+  assign Valid = ValidBits[RAdrD];
+
   generate
     if(DIRTY_BITS) begin
 
       always_ff @(posedge clk, posedge reset) begin
 	if (reset) 
   	  DirtyBits <= {NUMLINES{1'b0}};
-	else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1;
-	else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0;
+	else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1;
+	else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0;
       end
 
-      always_ff @(posedge clk) begin
-	Dirty <= DirtyBits[RAdr];
+      always_ff @(posedge clk, posedge reset) begin
+	SetDirtyD <= SetDirty;
+	ClearDirtyD <= ClearDirty;
       end
 
+      assign Dirty = DirtyBits[RAdrD];
+
     end else begin
       assign Dirty = 1'b0;
     end