diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv
index d2739a7c..e02c3675 100644
--- a/wally-pipelined/src/cache/cachereplacementpolicy.sv
+++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv
@@ -49,7 +49,7 @@ module cachereplacementpolicy
   logic 					LRUWriteEnD;
   
   /* verilator lint_off BLKLOOPINIT */
-  always_ff @(posedge clk, posedge reset) begin
+  always_ff @(posedge clk) begin
     if (reset) begin
       RAdrD <= '0;
       MemPAdrMD <= '0;
diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv
index bb760bba..6f9c0855 100644
--- a/wally-pipelined/src/cache/cacheway.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -111,7 +111,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay;
     
   
-  always_ff @(posedge clk, posedge reset) begin
+  always_ff @(posedge clk) begin
     if (reset) 
   	ValidBits <= {NUMLINES{1'b0}};
     else if (InvalidateAll) 
@@ -134,14 +134,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 
   generate
     if(DIRTY_BITS) begin
-      always_ff @(posedge clk, posedge reset) begin
+      always_ff @(posedge clk) begin
 	if (reset) 
   	  DirtyBits <= {NUMLINES{1'b0}};
 	else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1;
 	else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0;
       end
 
-      always_ff @(posedge clk, posedge reset) begin
+      always_ff @(posedge clk) begin
 	SetDirtyD <= SetDirty;
 	ClearDirtyD <= ClearDirty;
       end
diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index 4fba55bd..59f90462 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -144,7 +144,7 @@ module dcachefsm
   assign CntEn = PreCntEn & AHBAck;
 
 
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
     else CurrState <= #1 NextState;  
   
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 82590747..2461e0dd 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -116,7 +116,7 @@ module icachefsm
   logic 		       PreCntEn;
 
   // the FSM is always runing, do not stall.
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
     else CurrState <= #1 NextState;
 
diff --git a/wally-pipelined/src/ifu/RAsPredictor.sv b/wally-pipelined/src/ifu/RAsPredictor.sv
index bde30be5..44929e3c 100644
--- a/wally-pipelined/src/ifu/RAsPredictor.sv
+++ b/wally-pipelined/src/ifu/RAsPredictor.sv
@@ -62,7 +62,7 @@ module RASPredictor
 			   .q(PtrQ));
 
   // RAS must be reset. 
-  always_ff @ (posedge clk, posedge reset) begin
+  always_ff @ (posedge clk) begin
     if(reset) begin
       for(index=0; index<StackSize; index++)
 	memory[index] <= {`XLEN{1'b0}};