From c3d07b2c46bdb2b43071e03826b0367e1ec111ff Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Mon, 4 Apr 2022 17:17:12 +0000 Subject: [PATCH] generating all testfloat vectors --- addins/riscv-arch-test | 2 +- pipelined/config/buildroot/wally-config.vh | 1 + pipelined/config/fpga/wally-config.vh | 1 + pipelined/config/rv32e/wally-config.vh | 1 + pipelined/config/rv32gc/wally-config.vh | 1 + pipelined/config/rv32ic/wally-config.vh | 1 + pipelined/config/rv64BP/wally-config.vh | 1 + pipelined/config/rv64fp/wally-config.vh | 1 + pipelined/config/rv64gc/wally-config.vh | 1 + pipelined/config/rv64ic/wally-config.vh | 1 + pipelined/config/shared/wally-shared.vh | 4 - pipelined/fpu-testfloat/FMA/tbgen/tb.sv | 332 ------------ pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh | 3 - pipelined/src/fpu/fcmp.sv | 1 + pipelined/testbench/fp/tests/fma-testbench.sv | 279 ---------- pipelined/testbench/fp/tests/fma.do | 50 -- pipelined/testbench/fp/tests/sim-fma | 1 - pipelined/testbench/fp/tests/sim-fma-batch | 1 - tests/fp/append_ctrlSig.sh | 484 ++++++++++++++++++ tests/fp/create_vectors.sh | 483 +++++++++++++++++ tests/fp/create_vectors128fma.sh | 31 -- tests/fp/create_vectors16.sh | 31 -- tests/fp/create_vectors16fma.sh | 31 -- tests/fp/create_vectors32.sh | 29 -- tests/fp/create_vectors32_64.sh | 20 - tests/fp/create_vectors32cmp.sh | 13 - tests/fp/create_vectors32fma.sh | 31 -- tests/fp/create_vectors64.sh | 30 -- tests/fp/create_vectors64_32.sh | 22 - tests/fp/create_vectors64cmp.sh | 13 - tests/fp/create_vectors64fma.sh | 31 -- tests/fp/create_vectorsi.sh | 64 --- tests/fp/remove_spaces.sh | 483 +++++++++++++++++ tests/fp/run_all.sh | 15 +- tests/fp/undy.sh | 2 - 35 files changed, 1464 insertions(+), 1031 deletions(-) delete mode 100644 pipelined/fpu-testfloat/FMA/tbgen/tb.sv delete mode 100755 pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh delete mode 100644 pipelined/testbench/fp/tests/fma-testbench.sv delete mode 100644 pipelined/testbench/fp/tests/fma.do delete mode 100755 pipelined/testbench/fp/tests/sim-fma delete mode 100755 pipelined/testbench/fp/tests/sim-fma-batch create mode 100755 tests/fp/append_ctrlSig.sh create mode 100755 tests/fp/create_vectors.sh delete mode 100755 tests/fp/create_vectors128fma.sh delete mode 100755 tests/fp/create_vectors16.sh delete mode 100755 tests/fp/create_vectors16fma.sh delete mode 100755 tests/fp/create_vectors32.sh delete mode 100755 tests/fp/create_vectors32_64.sh delete mode 100755 tests/fp/create_vectors32cmp.sh delete mode 100755 tests/fp/create_vectors32fma.sh delete mode 100755 tests/fp/create_vectors64.sh delete mode 100755 tests/fp/create_vectors64_32.sh delete mode 100755 tests/fp/create_vectors64cmp.sh delete mode 100755 tests/fp/create_vectors64fma.sh delete mode 100755 tests/fp/create_vectorsi.sh create mode 100755 tests/fp/remove_spaces.sh delete mode 100755 tests/fp/undy.sh diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index effd553a..be67c99b 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 39048116..7587a9f2 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -40,6 +40,7 @@ `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1 +`define ZFH_SUPPORTED 0 `define COUNTERS 32 `define DESIGN_COMPILER 0 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index a7e94081..fc63937c 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -41,6 +41,7 @@ `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1 +`define ZFH_SUPPORTED 0 `define COUNTERS 32 `define DESIGN_COMPILER 0 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index ccbcb728..42e20aff 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -43,6 +43,7 @@ `define ZIFENCEI_SUPPORTED 0 `define COUNTERS 0 `define ZICOUNTERS_SUPPORTED 0 +`define ZFH_SUPPORTED 0 // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 07bc2010..022447ff 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -42,6 +42,7 @@ `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 +`define ZFH_SUPPORTED 0 // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 53669422..fcd3c8e5 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -42,6 +42,7 @@ `define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 0 +`define ZFH_SUPPORTED 0 // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 892794e0..005a1de3 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -44,6 +44,7 @@ `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 +`define ZFH_SUPPORTED 0 // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index 249af848..d25827b7 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -43,6 +43,7 @@ `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 +`define ZFH_SUPPORTED 0 /// Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index a3f1f794..6af3c7bd 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -43,6 +43,7 @@ `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 +`define ZFH_SUPPORTED 0 /// Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 10dcf34c..c46dbfe7 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -43,6 +43,7 @@ `define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 0 +`define ZFH_SUPPORTED 0 // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 198a4ab2..1538c521 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -50,10 +50,6 @@ // Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) `define PMPCFG_ENTRIES (`PMP_ENTRIES/8) - -// Floating-point half-precision -`define ZFH_SUPPORTED 0 - // Floating point constants for Quad, Double, Single, and Half precisions `define Q_LEN 128 `define Q_NE 15 diff --git a/pipelined/fpu-testfloat/FMA/tbgen/tb.sv b/pipelined/fpu-testfloat/FMA/tbgen/tb.sv deleted file mode 100644 index 5532aa63..00000000 --- a/pipelined/fpu-testfloat/FMA/tbgen/tb.sv +++ /dev/null @@ -1,332 +0,0 @@ - -`include "../../../config/old/rv64icfd/wally-config.vh" - -// `define FLEN (`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : `F_SUPPORTED ? 32 : 16) -// `define NE (`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : `F_SUPPORTED ? 8 : 5) -// `define NF (`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : `F_SUPPORTED ? 23 : 10) -// `define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) -// `define BIAS (`Q_SUPPORTED ? 16383 : `D_SUPPORTED ? 1023 : `F_SUPPORTED ? 127 : 15) -// `define XLEN 64 -// `define IEEE754 1 -`define Q_SUPPORTED 1 -// `define D_SUPPORTED 0 -// `define F_SUPPORTED 0 -`define H_SUPPORTED 0 -`define FPSIZES ((`Q_SUPPORTED&`D_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) ? 4 : (`Q_SUPPORTED&`D_SUPPORTED&`F_SUPPORTED) | (`Q_SUPPORTED&`D_SUPPORTED&`H_SUPPORTED) | (`Q_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) | (`D_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) ? 3 : (`Q_SUPPORTED&`D_SUPPORTED) | (`Q_SUPPORTED&`F_SUPPORTED) | (`Q_SUPPORTED&`H_SUPPORTED) | (`D_SUPPORTED&`F_SUPPORTED) | (`D_SUPPORTED&`H_SUPPORTED) | (`F_SUPPORTED&`H_SUPPORTED) ? 2 : 1) -`define LEN1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 64 : (`F_SUPPORTED & (`FLEN !== 32)) ? 32 : 16) -`define NE1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 11 : (`F_SUPPORTED & (`FLEN !== 32)) ? 8 : 5) -`define NF1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 52 : (`F_SUPPORTED & (`FLEN !== 32)) ? 23 : 10) -`define FMT1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 1 : (`F_SUPPORTED & (`FLEN !== 32)) ? 0 : 2) -`define BIAS1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 1023 : (`F_SUPPORTED & (`FLEN !== 32)) ? 127 : 15) -`define LEN2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 32 : 16) -`define NE2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 8 : 5) -`define NF2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 23 : 10) -`define FMT2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 0 : 2) -`define BIAS2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 127 : 15) -`define LEN3 16 -`define NE3 5//make constants for the constants ie 11/8/5 ect -`define NF3 10 // always support less hten max - maybe halfs -`define FMT3 2 -`define BIAS3 15 -module testbench3(); - - logic [31:0] errors=0; - logic [31:0] vectornum=0; - logic [`FLEN*4+7:0] testvectors[6133248:0]; - -// logic [63:0] X,Y,Z; - logic [`FLEN-1:0] ans; - logic [7:0] flags; - logic [2:0] FrmE; - logic [`FPSIZES/3:0] FmtE; - logic [`FLEN-1:0] FMAResM; - logic [4:0] FMAFlgM; -logic [2:0] FOpCtrlE; -logic [2*`NF+1:0] ProdManE; -logic [3*`NF+5:0] AlignedAddendE; -logic [`NE+1:0] ProdExpE; -logic AddendStickyE; -logic KillProdE; - -logic wnan; -logic ansnan, clk; - - -assign FOpCtrlE = 3'b0; - -// nearest even - 000 -// twords zero - 001 -// down - 010 -// up - 011 -// nearest max mag - 100 -assign FrmE = 3'b010; -assign FmtE = (`FPSIZES/3+1)'(1); - - logic [`FLEN-1:0] X, Y, Z; - // logic FmtE; - // logic [2:0] FOpCtrlE; - logic XSgnE, YSgnE, ZSgnE; - logic [`NE-1:0] XExpE, YExpE, ZExpE; - logic [`NF:0] XManE, YManE, ZManE; - logic XNormE; - logic XExpMaxE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; - logic XZeroE, YZeroE, ZZeroE; - logic [`NE-1:0] BiasE; - logic XInfE, YInfE, ZInfE; - logic [`FLEN-1:0] Addend; // value to add (Z or zero) - logic YExpMaxE, ZExpMaxE, Mult; // input exponent all 1s - - assign Mult = 1'b0; - unpacking unpacking(.*); - -// assign wnan = XNaNE|YNaNE|ZNaNE; -// assign ansnan = FmtE ? &ans[`FLEN-2:`NF] && |ans[`NF-1:0] : &ans[30:23] && |ans[22:0]; - - if (`FPSIZES === 1) begin - assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]); - assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); - end else if (`FPSIZES === 2) begin - assign ansnan = FmtE ? &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]) : &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]); - assign wnan = FmtE ? &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]) : &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); - end else if (`FPSIZES === 3) begin - always_comb begin - case (FmtE) - `FMT: begin - assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]); - assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); - - end - `FMT1: begin - assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]); - assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); - - end - `FMT2: begin - assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]); - assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]); - end - default: begin - assign ansnan = 0; - assign wnan = 0; - end - endcase - end - - end else begin - always_comb begin - case (FmtE) - `FMT: begin - assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]); - assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); - - end - `FMT1: begin - assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]); - assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); - - end - `FMT2: begin - assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]); - assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]); - end - `FMT3: begin - assign ansnan = &ans[`LEN3-2:`NF3]&(|ans[`NF3-1:0]); - assign wnan = &FMAResM[`LEN3-2:`NF3]&(|FMAResM[`NF3-1:0]); - end - endcase - end - end - // instantiate device under test - - logic [3*`NF+5:0] SumE, SumM; - logic InvZE, InvZM; - logic NegSumE, NegSumM; - logic ZSgnEffE, ZSgnEffM; - logic PSgnE, PSgnM; - logic [$clog2(3*`NF+7)-1:0] NormCntE, NormCntM; - - fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, - .FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, - .ProdExpE, .AddendStickyE, .KillProdE); -fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM(XManE), .YManM(YManE), .ZManM(ZManE), .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE), - // .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM, - .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), - .FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM, .Mult); - - - // produce clock - always - begin - clk = 1; #5; clk = 0; #5; - end - // at start of test, load vectors - // and pulse reset - initial - begin - $readmemh("testFloatNoSpace", testvectors); - end - // apply test vectors on rising edge of clk -always @(posedge clk) - begin - #1; - if (`FPSIZES === 3 | `FPSIZES === 4) begin - if (FmtE==2'b11) {X, Y, Z, ans, flags} = testvectors[vectornum]; - else if (FmtE==2'b01) begin - X = {{`FLEN-64{1'b1}}, testvectors[vectornum][263:200]}; - Y = {{`FLEN-64{1'b1}}, testvectors[vectornum][199:136]}; - Z = {{`FLEN-64{1'b1}}, testvectors[vectornum][135:72]}; - ans = {{`FLEN-64{1'b1}}, testvectors[vectornum][71:8]}; - flags = testvectors[vectornum][7:0]; - end - else if (FmtE==2'b00) begin - X = {{`FLEN-32{1'b1}}, testvectors[vectornum][135:104]}; - Y = {{`FLEN-32{1'b1}}, testvectors[vectornum][103:72]}; - Z = {{`FLEN-32{1'b1}}, testvectors[vectornum][71:40]}; - ans = {{`FLEN-32{1'b1}}, testvectors[vectornum][39:8]}; - flags = testvectors[vectornum][7:0]; - end - else begin - X = {{`FLEN-16{1'b1}}, testvectors[vectornum][71:56]}; - Y = {{`FLEN-16{1'b1}}, testvectors[vectornum][55:40]}; - Z = {{`FLEN-16{1'b1}}, testvectors[vectornum][39:24]}; - ans = {{`FLEN-16{1'b1}}, testvectors[vectornum][23:8]}; - flags = testvectors[vectornum][7:0]; - end - end - else begin - if (FmtE==1'b1) {X, Y, Z, ans, flags} = testvectors[vectornum]; - else if (FmtE==1'b0) begin - X = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+4*(`LEN1)-1:8+3*(`LEN1)]}; - Y = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+3*(`LEN1)-1:8+2*(`LEN1)]}; - Z = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+2*(`LEN1)-1:8+(`LEN1)]}; - ans = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+(`LEN1-1):8]}; - flags = testvectors[vectornum][7:0]; - end - end - end - // check results on falling edge of clk - always @(negedge clk) begin - if (`FPSIZES === 1 | `FPSIZES === 2) begin - if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]})) || (ZNaNE && (FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0]))))) begin - // fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w"); - // if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (FMAResM !== ans))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(XDenormE) $display( "xdenorm "); - if(YDenormE) $display( "ydenorm "); - if(ZDenormE) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf "); - if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf "); - if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); - if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); - if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf "); - if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf "); - if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN "); - if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN "); - errors = errors + 1; - //if (errors === 10) - $stop; - end - if((FmtE==1'b0)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[`LEN1-2:0] === {X[`LEN1-2:`NF1],1'b1,X[`NF1-2:0]})) || (YNaNE && (FMAResM[`LEN1-2:0] === {Y[`LEN1-2:`NF1],1'b1,Y[`NF1-2:0]})) || (ZNaNE && (FMAResM[`LEN1-2:0] === {Z[`LEN1-2:`NF1],1'b1,Z[`NF1-2:0]})) || (FMAResM[`LEN1-2:0] === ans[`LEN1-2:0]))) ))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); - if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); - errors = errors + 1; - // if (errors === 9) - $stop; - end - end else begin - - if((FmtE==2'b11) & (FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]})) || (ZNaNE && (FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0]))))) begin - // fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w"); - // if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (FMAResM !== ans))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(XDenormE) $display( "xdenorm "); - if(YDenormE) $display( "ydenorm "); - if(ZDenormE) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf "); - if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf "); - if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); - if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); - if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf "); - if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf "); - if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN "); - if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN "); - errors = errors + 1; - //if (errors === 10) - $stop; - end - if((FmtE==1'b01)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[64-2:0] === {X[64-2:52],1'b1,X[52-2:0]})) || (YNaNE && (FMAResM[64-2:0] === {Y[64-2:52],1'b1,Y[52-2:0]})) || (ZNaNE && (FMAResM[64-2:0] === {Z[64-2:52],1'b1,Z[52-2:0]})) || (FMAResM[62:0] === ans[62:0]))) ))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); - if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); - errors = errors + 1; - // if (errors === 9) - $stop; - end - if((FmtE==2'b00)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[32-2:0] === {X[32-2:23],1'b1,X[23-2:0]})) || (YNaNE && (FMAResM[32-2:0] === {Y[32-2:23],1'b1,Y[23-2:0]})) || (ZNaNE && (FMAResM[32-2:0] === {Z[32-2:23],1'b1,Z[23-2:0]})) || (FMAResM[30:0] === ans[30:0]))) ))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); - if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); - errors = errors + 1; - // if (errors === 9) - $stop; - end - if((FmtE==2'b10)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[16-2:0] === {X[16-2:10],1'b1,X[10-2:0]})) || (YNaNE && (FMAResM[16-2:0] === {Y[16-2:10],1'b1,Y[10-2:0]})) || (ZNaNE && (FMAResM[16-2:0] === {Z[16-2:10],1'b1,Z[10-2:0]})) || (FMAResM[14:0] === ans[14:0]))) ))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); - if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); - errors = errors + 1; - // if (errors === 9) - $stop; - end - end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 194'bx) begin - $display("%d tests completed with %d errors", vectornum, errors); - $stop; - end - end -endmodule diff --git a/pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh b/pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh deleted file mode 100755 index 8620f3b0..00000000 --- a/pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh +++ /dev/null @@ -1,3 +0,0 @@ -testfloat_gen f128_mulAdd -tininessafter -n 6133248 -rmin -seed 113355 -level 1 > testFloat -tr -d ' ' < testFloat > testFloatNoSpace - diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 61f37b00..b1486ea0 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -70,6 +70,7 @@ module fcmp ( if(`IEEE754) assign QNaN = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]}; else assign QNaN = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0}; + // when one input is a NaN -output the non-NaN always_comb begin case (FOpCtrlE[2:0]) 3'b111: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Min diff --git a/pipelined/testbench/fp/tests/fma-testbench.sv b/pipelined/testbench/fp/tests/fma-testbench.sv deleted file mode 100644 index 6ce50387..00000000 --- a/pipelined/testbench/fp/tests/fma-testbench.sv +++ /dev/null @@ -1,279 +0,0 @@ - -`include "wally-config.vh" -`define PATH "../../../../tests/fp/vectors/" - -string tests[] = '{ - "f16_mulAdd_rne.tv", - "f16_mulAdd_rz.tv", - "f16_mulAdd_ru.tv", - "f16_mulAdd_rd.tv", - "f16_mulAdd_rnm.tv", - "f32_mulAdd_rne.tv", - "f32_mulAdd_rz.tv", - "f32_mulAdd_ru.tv", - "f32_mulAdd_rd.tv", - "f32_mulAdd_rnm.tv", - "f64_mulAdd_rne.tv", - "f64_mulAdd_rz.tv", - "f64_mulAdd_ru.tv", - "f64_mulAdd_rd.tv", - "f64_mulAdd_rnm.tv", - "f128_mulAdd_rne.tv", - "f128_mulAdd_rz.tv", - "f128_mulAdd_ru.tv", - "f128_mulAdd_rd.tv", - "f128_mulAdd_rnm.tv" -}; - -// steps to run FMA tests -// 1) create test vectors in riscv-wally/tests/fp with: ./run-all.sh -// 2) go to riscv-wally/pipelined/testbench/fp/tests -// 3) run ./sim-wally-batch - -module fmatestbench(); - - logic clk; - logic [31:0] errors=0; - logic [31:0] vectornum=0; - logic [`FLEN*4+7+4+4:0] testvectors[6133248:0]; - int i = `ZFH_SUPPORTED ? 0 : `F_SUPPORTED ? 5 : `D_SUPPORTED ? 10 : 15; // set i to the first test that is run - - logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat - logic [`FLEN-1:0] ans; // result from TestFloat - logic [7:0] flags; // flags read form testfloat - logic [2:0] FrmE; // rounding mode - logic [`FPSIZES/3:0] FmtE; // format - 10 = half, 00 = single, 01 = double, 11 = quad - logic [3:0] FrmRead; // rounding mode read from testfloat - logic [3:0] FmtRead; // format read from testfloat - logic [`FLEN-1:0] FMAResM; // FMA's outputed result - logic [4:0] FMAFlgM; // FMA's outputed flags - logic [2:0] FOpCtrlE; // which opperation - logic wnan; // is the outputed result NaN - logic ansnan; // is the correct answer NaN - - // signals needed to connect modules - logic [`NE+1:0] ProdExpE; - logic AddendStickyE; - logic KillProdE; - logic XSgnE, YSgnE, ZSgnE; - logic [`NE-1:0] XExpE, YExpE, ZExpE; - logic [`NF:0] XManE, YManE, ZManE; - logic XNormE; - logic XExpMaxE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; - logic XInfE, YInfE, ZInfE; - logic XZeroE, YZeroE, ZZeroE; - logic YExpMaxE, ZExpMaxE, Mult; - logic [3*`NF+5:0] SumE; - logic InvZE; - logic NegSumE; - logic ZSgnEffE; - logic PSgnE; - logic [$clog2(3*`NF+7)-1:0] NormCntE; - - - assign FOpCtrlE = 3'b0; // set to 0 because test float only tests fMADD - assign Mult = 1'b0; // set to zero because not testing multiplication - - // check if the calculated result or correct answer is NaN - always_comb begin - case (FmtRead) - 4'b11: begin // quad - assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]); - assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); - - end - 4'b01: begin // double - assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]); - assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); - - end - 4'b00: begin // single - assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]); - assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]); - end - 4'b10: begin // half - assign ansnan = &ans[`H_LEN-2:`H_NF]&(|ans[`H_NF-1:0]); - assign wnan = &FMAResM[`H_LEN-2:`H_NF]&(|FMAResM[`H_NF-1:0]); - end - endcase - end - - // instantiate devices under test - unpack unpack(.X, .Y, .Z, .FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, - .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, - .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, - .XExpMaxE); - fma1 fma1(.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, - .FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, - .ProdExpE, .AddendStickyE, .KillProdE); - fma2 fma2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM(XManE), .YManM(YManE), .ZManM(ZManE), - .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), - .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE), .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), - .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(FmtE), .FrmM(FrmE), - .FMAFlgM, .FMAResM, .Mult); - - - // produce clock - always begin - clk = 1; #5; clk = 0; #5; - end - - // Read first test - initial begin - $display("\n\nRunning %s vectors", tests[i]); - $readmemh({`PATH, tests[i]}, testvectors); - end - - // apply test vectors on rising edge of clk - always @(posedge clk) begin - #1; - flags = testvectors[vectornum][15:8]; - FrmRead = testvectors[vectornum][7:4]; - FmtRead = testvectors[vectornum][3:0]; - if (FmtRead==4'b11 & `Q_SUPPORTED) begin // quad - X = testvectors[vectornum][16+4*(`Q_LEN)-1:16+3*(`Q_LEN)]; - Y = testvectors[vectornum][16+3*(`Q_LEN)-1:16+2*(`Q_LEN)]; - Z = testvectors[vectornum][16+2*(`Q_LEN)-1:16+`Q_LEN]; - ans = testvectors[vectornum][16+(`Q_LEN-1):16]; - end - else if (FmtRead==4'b01 & `D_SUPPORTED) begin // double - X = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+4*(`D_LEN)-1:16+3*(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+3*(`D_LEN)-1:16+2*(`D_LEN)]}; - Z = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+2*(`D_LEN)-1:16+`D_LEN]}; - ans = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+(`D_LEN-1):16]}; - end - else if (FmtRead==4'b00 & `F_SUPPORTED) begin // single - X = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+4*(`S_LEN)-1:16+3*(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+3*(`S_LEN)-1:16+2*(`S_LEN)]}; - Z = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+2*(`S_LEN)-1:16+`S_LEN]}; - ans = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+(`S_LEN-1):16]}; - end - else if (FmtRead==4'b10 & `ZFH_SUPPORTED) begin // half - X = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+4*(`H_LEN)-1:16+3*(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+3*(`H_LEN)-1:16+2*(`H_LEN)]}; - Z = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+2*(`H_LEN)-1:16+`H_LEN]}; - ans = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+(`H_LEN-1):16]}; - end - else begin - X = {`FLEN{1'bx}}; - Y = {`FLEN{1'bx}}; - Z = {`FLEN{1'bx}}; - ans = {`FLEN{1'bx}}; - end - - // trim format and rounding mode to appropriate size - if (`FPSIZES <= 2) FmtE = FmtRead === `FMT; // rewrite format if 2 or less floating formats are supported - else FmtE = FmtRead[1:0]; - FrmE = FrmRead[2:0]; - end - - // check results on falling edge of clk - always @(negedge clk) begin - // quad - if((FmtRead==4'b11) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0] | (XNaNE&(FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) | (YNaNE&(FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]})) | (ZNaNE&(FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})))))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(XDenormE) $display( "xdenorm "); - if(YDenormE) $display( "ydenorm "); - if(ZDenormE) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf "); - if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf "); - if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); - if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); - if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf "); - if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf "); - if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN "); - if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN "); - errors = errors + 1; - if (errors === 1) $stop; - end - // double - if((FmtRead==4'b01) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`D_LEN-2:0] === ans[`D_LEN-2:0] | (XNaNE&(FMAResM[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaNE&(FMAResM[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | (ZNaNE&(FMAResM[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]})))))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); - if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); - errors = errors + 1; - if (errors === 1) $stop; - end - // single - if((FmtRead==4'b00) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`S_LEN-2:0] === ans[`S_LEN-2:0] | (XNaNE&(FMAResM[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaNE&(FMAResM[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | (ZNaNE&(FMAResM[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]})))))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); - if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); - errors = errors + 1; - if (errors === 1) $stop; - end - // half - if((FmtRead==4'b01) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`H_LEN-2:0] === ans[`H_LEN-2:0] | (XNaNE&(FMAResM[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | (YNaNE&(FMAResM[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | (ZNaNE&(FMAResM[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]})))))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); - if(FMAFlgM[4] !== 0) $display( "invld "); - if(FMAFlgM[2] !== 0) $display( "ovrflw "); - if(FMAFlgM[1] !== 0) $display( "unflw "); - if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); - if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); - errors = errors + 1; - if (errors === 1) $stop; - end - - // if ( vectornum === 3165862) $stop; // uncomment for specific test - vectornum = vectornum + 1; // increment test - if (testvectors[vectornum][0] === 1'bx) begin // if reached the end of file - if (errors) begin // if there were errors - $display("%s completed with %d tests and %d errors", tests[i], vectornum, errors); - $stop; - end - else begin // if no errors - if(tests[i] === "") begin // if no more tests - $display("\nAll tests completed with %d errors\n", errors); - $stop; - end - - $display("%s completed successfully with %d tests and %d errors (across all tests)\n", tests[i], vectornum, errors); - - // increment tests - skip some precisions if needed - if ((i === 4 & ~`F_SUPPORTED) | (i === 9 & ~`D_SUPPORTED) | (i === 14 & ~`Q_SUPPORTED)) i = i+5; - if ((i === 9 & ~`D_SUPPORTED) | (i === 14 & ~`Q_SUPPORTED)) i = i+5; - if ((i === 14 & ~`Q_SUPPORTED)) i = i+5; - i = i+1; - - // if no more tests - finish - if(tests[i] === "") begin - $display("\nAll tests completed with %d errors\n", errors); - $stop; - end - - // read next files - $display("Running %s vectors", tests[i]); - $readmemh({`PATH, tests[i]}, testvectors); - vectornum = 0; - end - end - end -endmodule diff --git a/pipelined/testbench/fp/tests/fma.do b/pipelined/testbench/fp/tests/fma.do deleted file mode 100644 index 6349be0e..00000000 --- a/pipelined/testbench/fp/tests/fma.do +++ /dev/null @@ -1,50 +0,0 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -# $num = the added words after the call -vlog +incdir+../../../config/$1 +incdir+../../../config/shared fma-testbench.sv ../../../src/fpu/fma.sv ../../../src/fpu/unpack.sv -suppress 2583 -suppress 7063 - -vsim -voptargs=+acc work.fmatestbench - -view wave -#-- display input and output signals as hexidecimal values -#do ./wave-dos/peripheral-waves.do -#add log -recursive /* -#do wave.do deal with when ready - -#-- Run the Simulation -#run 3600 -run -all -noview fma-testbench.sv -view wave - diff --git a/pipelined/testbench/fp/tests/sim-fma b/pipelined/testbench/fp/tests/sim-fma deleted file mode 100755 index 5027d43e..00000000 --- a/pipelined/testbench/fp/tests/sim-fma +++ /dev/null @@ -1 +0,0 @@ -vsim -do "do fma.do rv64fp" diff --git a/pipelined/testbench/fp/tests/sim-fma-batch b/pipelined/testbench/fp/tests/sim-fma-batch deleted file mode 100755 index 321e0678..00000000 --- a/pipelined/testbench/fp/tests/sim-fma-batch +++ /dev/null @@ -1 +0,0 @@ -vsim -c -do "do fma.do rv64fp" \ No newline at end of file diff --git a/tests/fp/append_ctrlSig.sh b/tests/fp/append_ctrlSig.sh new file mode 100755 index 00000000..2cf1dc17 --- /dev/null +++ b/tests/fp/append_ctrlSig.sh @@ -0,0 +1,484 @@ +#!/bin/sh +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" +OUTPUT="./vectors" +echo "Editing ui32_to_f16 test vectors" +sed -ie 's/$/_0_2_2/' $OUTPUT/ui32_to_f16_rne.tv +sed -ie 's/$/_1_2_2/' $OUTPUT/ui32_to_f16_rz.tv +sed -ie 's/$/_3_2_2/' $OUTPUT/ui32_to_f16_ru.tv +sed -ie 's/$/_2_2_2/' $OUTPUT/ui32_to_f16_rd.tv +sed -ie 's/$/_4_2_2/' $OUTPUT/ui32_to_f16_rnm.tv +echo "Editing ui32_to_f32 test vectors" +sed -ie 's/$/_0_0_2/' $OUTPUT/ui32_to_f32_rne.tv +sed -ie 's/$/_1_0_2/' $OUTPUT/ui32_to_f32_rz.tv +sed -ie 's/$/_3_0_2/' $OUTPUT/ui32_to_f32_ru.tv +sed -ie 's/$/_2_0_2/' $OUTPUT/ui32_to_f32_rd.tv +sed -ie 's/$/_4_0_2/' $OUTPUT/ui32_to_f32_rnm.tv +echo "Editing ui32_to_f64 test vectors" +sed -ie 's/$/_0_1_2/' $OUTPUT/ui32_to_f64_rne.tv +sed -ie 's/$/_1_1_2/' $OUTPUT/ui32_to_f64_rz.tv +sed -ie 's/$/_3_1_2/' $OUTPUT/ui32_to_f64_ru.tv +sed -ie 's/$/_2_1_2/' $OUTPUT/ui32_to_f64_rd.tv +sed -ie 's/$/_4_1_2/' $OUTPUT/ui32_to_f64_rnm.tv +echo "Editing ui32_to_f128 test vectors" +sed -ie 's/$/_0_3_2/' $OUTPUT/ui32_to_f128_rne.tv +sed -ie 's/$/_1_3_2/' $OUTPUT/ui32_to_f128_rz.tv +sed -ie 's/$/_3_3_2/' $OUTPUT/ui32_to_f128_ru.tv +sed -ie 's/$/_2_3_2/' $OUTPUT/ui32_to_f128_rd.tv +sed -ie 's/$/_4_3_2/' $OUTPUT/ui32_to_f128_rnm.tv +echo "Editing ui64_to_f16 test vectors" +sed -ie 's/$/_0_2_6/' $OUTPUT/ui64_to_f16_rne.tv +sed -ie 's/$/_1_2_6/' $OUTPUT/ui64_to_f16_rz.tv +sed -ie 's/$/_3_2_6/' $OUTPUT/ui64_to_f16_ru.tv +sed -ie 's/$/_2_2_6/' $OUTPUT/ui64_to_f16_rd.tv +sed -ie 's/$/_4_2_6/' $OUTPUT/ui64_to_f16_rnm.tv +echo "Editing ui64_to_f32 test vectors" +sed -ie 's/$/_0_0_6/' $OUTPUT/ui64_to_f32_rne.tv +sed -ie 's/$/_1_0_6/' $OUTPUT/ui64_to_f32_rz.tv +sed -ie 's/$/_3_0_6/' $OUTPUT/ui64_to_f32_ru.tv +sed -ie 's/$/_2_0_6/' $OUTPUT/ui64_to_f32_rd.tv +sed -ie 's/$/_4_0_6/' $OUTPUT/ui64_to_f32_rnm.tv +echo "Editing ui64_to_f64 test vectors" +sed -ie 's/$/_0_1_6/' $OUTPUT/ui64_to_f64_rne.tv +sed -ie 's/$/_1_1_6/' $OUTPUT/ui64_to_f64_rz.tv +sed -ie 's/$/_3_1_6/' $OUTPUT/ui64_to_f64_ru.tv +sed -ie 's/$/_2_1_6/' $OUTPUT/ui64_to_f64_rd.tv +sed -ie 's/$/_4_1_6/' $OUTPUT/ui64_to_f64_rnm.tv +echo "Editing ui64_to_f128 test vectors" +sed -ie 's/$/_0_3_6/' $OUTPUT/ui64_to_f128_rne.tv +sed -ie 's/$/_1_3_6/' $OUTPUT/ui64_to_f128_rz.tv +sed -ie 's/$/_3_3_6/' $OUTPUT/ui64_to_f128_ru.tv +sed -ie 's/$/_2_3_6/' $OUTPUT/ui64_to_f128_rd.tv +sed -ie 's/$/_4_3_6/' $OUTPUT/ui64_to_f128_rnm.tv +echo "Editing i32_to_f16 test vectors" +sed -ie 's/$/_0_2_0/' $OUTPUT/i32_to_f16_rne.tv +sed -ie 's/$/_1_2_0/' $OUTPUT/i32_to_f16_rz.tv +sed -ie 's/$/_3_2_0/' $OUTPUT/i32_to_f16_ru.tv +sed -ie 's/$/_2_2_0/' $OUTPUT/i32_to_f16_rd.tv +sed -ie 's/$/_4_2_0/' $OUTPUT/i32_to_f16_rnm.tv +echo "Editing i32_to_f32 test vectors" +sed -ie 's/$/_0_0_0/' $OUTPUT/i32_to_f32_rne.tv +sed -ie 's/$/_1_0_0/' $OUTPUT/i32_to_f32_rz.tv +sed -ie 's/$/_3_0_0/' $OUTPUT/i32_to_f32_ru.tv +sed -ie 's/$/_2_0_0/' $OUTPUT/i32_to_f32_rd.tv +sed -ie 's/$/_4_0_0/' $OUTPUT/i32_to_f32_rnm.tv +echo "Editing i32_to_f64 test vectors" +sed -ie 's/$/_0_1_0/' $OUTPUT/i32_to_f64_rne.tv +sed -ie 's/$/_1_1_0/' $OUTPUT/i32_to_f64_rz.tv +sed -ie 's/$/_3_1_0/' $OUTPUT/i32_to_f64_ru.tv +sed -ie 's/$/_2_1_0/' $OUTPUT/i32_to_f64_rd.tv +sed -ie 's/$/_4_1_0/' $OUTPUT/i32_to_f64_rnm.tv +echo "Editing i32_to_f128 test vectors" +sed -ie 's/$/_0_3_0/' $OUTPUT/i32_to_f128_rne.tv +sed -ie 's/$/_1_3_0/' $OUTPUT/i32_to_f128_rz.tv +sed -ie 's/$/_3_3_0/' $OUTPUT/i32_to_f128_ru.tv +sed -ie 's/$/_2_3_0/' $OUTPUT/i32_to_f128_rd.tv +sed -ie 's/$/_4_3_0/' $OUTPUT/i32_to_f128_rnm.tv +echo "Editing i64_to_f16 test vectors" +sed -ie 's/$/_0_2_4/' $OUTPUT/i64_to_f16_rne.tv +sed -ie 's/$/_1_2_4/' $OUTPUT/i64_to_f16_rz.tv +sed -ie 's/$/_3_2_4/' $OUTPUT/i64_to_f16_ru.tv +sed -ie 's/$/_2_2_4/' $OUTPUT/i64_to_f16_rd.tv +sed -ie 's/$/_4_2_4/' $OUTPUT/i64_to_f16_rnm.tv +echo "Editing i64_to_f32 test vectors" +sed -ie 's/$/_0_0_4/' $OUTPUT/i64_to_f32_rne.tv +sed -ie 's/$/_1_0_4/' $OUTPUT/i64_to_f32_rz.tv +sed -ie 's/$/_3_0_4/' $OUTPUT/i64_to_f32_ru.tv +sed -ie 's/$/_2_0_4/' $OUTPUT/i64_to_f32_rd.tv +sed -ie 's/$/_4_0_4/' $OUTPUT/i64_to_f32_rnm.tv +echo "Editing i64_to_f64 test vectors" +sed -ie 's/$/_0_1_4/' $OUTPUT/i64_to_f64_rne.tv +sed -ie 's/$/_1_1_4/' $OUTPUT/i64_to_f64_rz.tv +sed -ie 's/$/_3_1_4/' $OUTPUT/i64_to_f64_ru.tv +sed -ie 's/$/_2_1_4/' $OUTPUT/i64_to_f64_rd.tv +sed -ie 's/$/_4_1_4/' $OUTPUT/i64_to_f64_rnm.tv +echo "Editing i64_to_f128 test vectors" +sed -ie 's/$/_0_3_4/' $OUTPUT/i64_to_f128_rne.tv +sed -ie 's/$/_1_3_4/' $OUTPUT/i64_to_f128_rz.tv +sed -ie 's/$/_3_3_4/' $OUTPUT/i64_to_f128_ru.tv +sed -ie 's/$/_2_3_4/' $OUTPUT/i64_to_f128_rd.tv +sed -ie 's/$/_4_3_4/' $OUTPUT/i64_to_f128_rnm.tv +echo "Editing f16_to_ui32 test vectors" +sed -ie 's/$/_0_2_3/' $OUTPUT/f16_to_ui32_rne.tv +sed -ie 's/$/_1_2_3/' $OUTPUT/f16_to_ui32_rz.tv +sed -ie 's/$/_3_2_3/' $OUTPUT/f16_to_ui32_ru.tv +sed -ie 's/$/_2_2_3/' $OUTPUT/f16_to_ui32_rd.tv +sed -ie 's/$/_4_2_3/' $OUTPUT/f16_to_ui32_rnm.tv +echo "Editing f32_to_ui32 test vectors" +sed -ie 's/$/_0_0_3/' $OUTPUT/f32_to_ui32_rne.tv +sed -ie 's/$/_1_0_3/' $OUTPUT/f32_to_ui32_rz.tv +sed -ie 's/$/_3_0_3/' $OUTPUT/f32_to_ui32_ru.tv +sed -ie 's/$/_2_0_3/' $OUTPUT/f32_to_ui32_rd.tv +sed -ie 's/$/_4_0_3/' $OUTPUT/f32_to_ui32_rnm.tv +echo "Editing f64_to_ui32 test vectors" +sed -ie 's/$/_0_1_3/' $OUTPUT/f64_to_ui32_rne.tv +sed -ie 's/$/_1_1_3/' $OUTPUT/f64_to_ui32_rz.tv +sed -ie 's/$/_3_1_3/' $OUTPUT/f64_to_ui32_ru.tv +sed -ie 's/$/_2_1_3/' $OUTPUT/f64_to_ui32_rd.tv +sed -ie 's/$/_4_1_3/' $OUTPUT/f64_to_ui32_rnm.tv +echo "Editing f128_to_ui32 test vectors" +sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_ui32_rne.tv +sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_ui32_rz.tv +sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_ui32_ru.tv +sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_ui32_rd.tv +sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_ui32_rnm.tv +echo "Editing f16_to_ui64 test vectors" +sed -ie 's/$/_0_2_7/' $OUTPUT/f16_to_ui64_rne.tv +sed -ie 's/$/_1_2_7/' $OUTPUT/f16_to_ui64_rz.tv +sed -ie 's/$/_3_2_7/' $OUTPUT/f16_to_ui64_ru.tv +sed -ie 's/$/_2_2_7/' $OUTPUT/f16_to_ui64_rd.tv +sed -ie 's/$/_4_2_7/' $OUTPUT/f16_to_ui64_rnm.tv +echo "Editing f32_to_ui64 test vectors" +sed -ie 's/$/_0_0_7/' $OUTPUT/f32_to_ui64_rne.tv +sed -ie 's/$/_1_0_7/' $OUTPUT/f32_to_ui64_rz.tv +sed -ie 's/$/_3_0_7/' $OUTPUT/f32_to_ui64_ru.tv +sed -ie 's/$/_2_0_7/' $OUTPUT/f32_to_ui64_rd.tv +sed -ie 's/$/_4_0_7/' $OUTPUT/f32_to_ui64_rnm.tv +echo "Editing f64_to_ui64 test vectors" +sed -ie 's/$/_0_1_7/' $OUTPUT/f64_to_ui64_rne.tv +sed -ie 's/$/_1_1_7/' $OUTPUT/f64_to_ui64_rz.tv +sed -ie 's/$/_3_1_7/' $OUTPUT/f64_to_ui64_ru.tv +sed -ie 's/$/_2_1_7/' $OUTPUT/f64_to_ui64_rd.tv +sed -ie 's/$/_4_1_7/' $OUTPUT/f64_to_ui64_rnm.tv +echo "Editing f128_to_ui64 test vectors" +sed -ie 's/$/_0_3_7/' $OUTPUT/f128_to_ui64_rne.tv +sed -ie 's/$/_1_3_7/' $OUTPUT/f128_to_ui64_rz.tv +sed -ie 's/$/_3_3_7/' $OUTPUT/f128_to_ui64_ru.tv +sed -ie 's/$/_2_3_7/' $OUTPUT/f128_to_ui64_rd.tv +sed -ie 's/$/_4_3_7/' $OUTPUT/f128_to_ui64_rnm.tv +echo "Editing f16_to_i32 test vectors" +sed -ie 's/$/_0_2_1/' $OUTPUT/f16_to_i32_rne.tv +sed -ie 's/$/_1_2_1/' $OUTPUT/f16_to_i32_rz.tv +sed -ie 's/$/_3_2_1/' $OUTPUT/f16_to_i32_ru.tv +sed -ie 's/$/_2_2_1/' $OUTPUT/f16_to_i32_rd.tv +sed -ie 's/$/_4_2_1/' $OUTPUT/f16_to_i32_rnm.tv +echo "Editing f32_to_i32 test vectors" +sed -ie 's/$/_0_0_1/' $OUTPUT/f32_to_i32_rne.tv +sed -ie 's/$/_1_0_1/' $OUTPUT/f32_to_i32_rz.tv +sed -ie 's/$/_3_0_1/' $OUTPUT/f32_to_i32_ru.tv +sed -ie 's/$/_2_0_1/' $OUTPUT/f32_to_i32_rd.tv +sed -ie 's/$/_4_0_1/' $OUTPUT/f32_to_i32_rnm.tv +echo "Editing f64_to_i32 test vectors" +sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_i32_rne.tv +sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_i32_rz.tv +sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_i32_ru.tv +sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_i32_rd.tv +sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_i32_rnm.tv +echo "Editing f128_to_i32 test vectors" +sed -ie 's/$/_0_3_1/' $OUTPUT/f128_to_i32_rne.tv +sed -ie 's/$/_1_3_1/' $OUTPUT/f128_to_i32_rz.tv +sed -ie 's/$/_3_3_1/' $OUTPUT/f128_to_i32_ru.tv +sed -ie 's/$/_2_3_1/' $OUTPUT/f128_to_i32_rd.tv +sed -ie 's/$/_4_3_1/' $OUTPUT/f128_to_i32_rnm.tv +echo "Editing f16_to_i64 test vectors" +sed -ie 's/$/_0_2_5/' $OUTPUT/f16_to_i64_rne.tv +sed -ie 's/$/_1_2_5/' $OUTPUT/f16_to_i64_rz.tv +sed -ie 's/$/_3_2_5/' $OUTPUT/f16_to_i64_ru.tv +sed -ie 's/$/_2_2_5/' $OUTPUT/f16_to_i64_rd.tv +sed -ie 's/$/_4_2_5/' $OUTPUT/f16_to_i64_rnm.tv +echo "Editing f32_to_i64 test vectors" +sed -ie 's/$/_0_0_5/' $OUTPUT/f32_to_i64_rne.tv +sed -ie 's/$/_1_0_5/' $OUTPUT/f32_to_i64_rz.tv +sed -ie 's/$/_3_0_5/' $OUTPUT/f32_to_i64_ru.tv +sed -ie 's/$/_2_0_5/' $OUTPUT/f32_to_i64_rd.tv +sed -ie 's/$/_4_0_5/' $OUTPUT/f32_to_i64_rnm.tv +echo "Editing f64_to_i64 test vectors" +sed -ie 's/$/_0_1_5/' $OUTPUT/f64_to_i64_rne.tv +sed -ie 's/$/_1_1_5/' $OUTPUT/f64_to_i64_rz.tv +sed -ie 's/$/_3_1_5/' $OUTPUT/f64_to_i64_ru.tv +sed -ie 's/$/_2_1_5/' $OUTPUT/f64_to_i64_rd.tv +sed -ie 's/$/_4_1_5/' $OUTPUT/f64_to_i64_rnm.tv +echo "Editing f128_to_i64 test vectors" +sed -ie 's/$/_0_3_5/' $OUTPUT/f128_to_i64_rne.tv +sed -ie 's/$/_1_3_5/' $OUTPUT/f128_to_i64_rz.tv +sed -ie 's/$/_3_3_5/' $OUTPUT/f128_to_i64_ru.tv +sed -ie 's/$/_2_3_5/' $OUTPUT/f128_to_i64_rd.tv +sed -ie 's/$/_4_3_5/' $OUTPUT/f128_to_i64_rnm.tv +echo "Editing f16_to_f32 test vectors" +sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f32_rne.tv +sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f32_rz.tv +sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f32_ru.tv +sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f32_rd.tv +sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f32_rnm.tv +echo "Editing f16_to_f64 test vectors" +sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f64_rne.tv +sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f64_rz.tv +sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f64_ru.tv +sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f64_rd.tv +sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f64_rnm.tv +echo "Editing f16_to_f128 test vectors" +sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f128_rne.tv +sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f128_rz.tv +sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f128_ru.tv +sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f128_rd.tv +sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f128_rnm.tv +echo "Editing f32_to_f16 test vectors" +sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f16_rne.tv +sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f16_rz.tv +sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f16_ru.tv +sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f16_rd.tv +sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f16_rnm.tv +echo "Editing f32_to_f64 test vectors" +sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f64_rne.tv +sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f64_rz.tv +sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f64_ru.tv +sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f64_rd.tv +sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f64_rnm.tv +echo "Editing f32_to_f128 test vectors" +sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f128_rne.tv +sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f128_rz.tv +sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f128_ru.tv +sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f128_rd.tv +sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f128_rnm.tv +echo "Editing f64_to_f16 test vectors" +sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f16_rne.tv +sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f16_rz.tv +sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f16_ru.tv +sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f16_rd.tv +sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f16_rnm.tv +echo "Editing f64_to_f32 test vectors" +sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f32_rne.tv +sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f32_rz.tv +sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f32_ru.tv +sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f32_rd.tv +sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f32_rnm.tv +echo "Editing f64_to_f128 test vectors" +sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f128_rne.tv +sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f128_rz.tv +sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f128_ru.tv +sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f128_rd.tv +sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f128_rnm.tv +echo "Editing f128_to_f16 test vectors" +sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f16_rne.tv +sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f16_rz.tv +sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f16_ru.tv +sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f16_rd.tv +sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f16_rnm.tv +echo "Editing f128_to_f32 test vectors" +sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f32_rne.tv +sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f32_rz.tv +sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f32_ru.tv +sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f32_rd.tv +sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f32_rnm.tv +echo "Editing f128_to_f64 test vectors" +sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f64_rne.tv +sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f64_rz.tv +sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f64_ru.tv +sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f64_rd.tv +sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f64_rnm.tv +echo "Editing f16_add test vectors" +sed -ie 's/$/_0_2_6/' $OUTPUT/f16_add_rne.tv +sed -ie 's/$/_1_2_6/' $OUTPUT/f16_add_rz.tv +sed -ie 's/$/_3_2_6/' $OUTPUT/f16_add_ru.tv +sed -ie 's/$/_2_2_6/' $OUTPUT/f16_add_rd.tv +sed -ie 's/$/_4_2_6/' $OUTPUT/f16_add_rnm.tv +echo "Editing f32_add test vectors" +sed -ie 's/$/_0_0_6/' $OUTPUT/f32_add_rne.tv +sed -ie 's/$/_1_0_6/' $OUTPUT/f32_add_rz.tv +sed -ie 's/$/_3_0_6/' $OUTPUT/f32_add_ru.tv +sed -ie 's/$/_2_0_6/' $OUTPUT/f32_add_rd.tv +sed -ie 's/$/_4_0_6/' $OUTPUT/f32_add_rnm.tv +echo "Editing f64_add test vectors" +sed -ie 's/$/_0_1_6/' $OUTPUT/f64_add_rne.tv +sed -ie 's/$/_1_1_6/' $OUTPUT/f64_add_rz.tv +sed -ie 's/$/_3_1_6/' $OUTPUT/f64_add_ru.tv +sed -ie 's/$/_2_1_6/' $OUTPUT/f64_add_rd.tv +sed -ie 's/$/_4_1_6/' $OUTPUT/f64_add_rnm.tv +echo "Editing f128_add test vectors" +sed -ie 's/$/_0_3_6/' $OUTPUT/f128_add_rne.tv +sed -ie 's/$/_1_3_6/' $OUTPUT/f128_add_rz.tv +sed -ie 's/$/_3_3_6/' $OUTPUT/f128_add_ru.tv +sed -ie 's/$/_2_3_6/' $OUTPUT/f128_add_rd.tv +sed -ie 's/$/_4_3_6/' $OUTPUT/f128_add_rnm.tv +echo "Editing f16_sub test vectors" +sed -ie 's/$/_0_2_7/' $OUTPUT/f16_sub_rne.tv +sed -ie 's/$/_1_2_7/' $OUTPUT/f16_sub_rz.tv +sed -ie 's/$/_3_2_7/' $OUTPUT/f16_sub_ru.tv +sed -ie 's/$/_2_2_7/' $OUTPUT/f16_sub_rd.tv +sed -ie 's/$/_4_2_7/' $OUTPUT/f16_sub_rnm.tv +echo "Editing f32_sub test vectors" +sed -ie 's/$/_0_0_7/' $OUTPUT/f32_sub_rne.tv +sed -ie 's/$/_1_0_7/' $OUTPUT/f32_sub_rz.tv +sed -ie 's/$/_3_0_7/' $OUTPUT/f32_sub_ru.tv +sed -ie 's/$/_2_0_7/' $OUTPUT/f32_sub_rd.tv +sed -ie 's/$/_4_0_7/' $OUTPUT/f32_sub_rnm.tv +echo "Editing f64_sub test vectors" +sed -ie 's/$/_0_1_7/' $OUTPUT/f64_sub_rne.tv +sed -ie 's/$/_1_1_7/' $OUTPUT/f64_sub_rz.tv +sed -ie 's/$/_3_1_7/' $OUTPUT/f64_sub_ru.tv +sed -ie 's/$/_2_1_7/' $OUTPUT/f64_sub_rd.tv +sed -ie 's/$/_4_1_7/' $OUTPUT/f64_sub_rnm.tv +echo "Editing f128_sub test vectors" +sed -ie 's/$/_0_3_7/' $OUTPUT/f128_sub_rne.tv +sed -ie 's/$/_1_3_7/' $OUTPUT/f128_sub_rz.tv +sed -ie 's/$/_3_3_7/' $OUTPUT/f128_sub_ru.tv +sed -ie 's/$/_2_3_7/' $OUTPUT/f128_sub_rd.tv +sed -ie 's/$/_4_3_7/' $OUTPUT/f128_sub_rnm.tv +echo "Editing f16_mul test vectors" +sed -ie 's/$/_0_2_4/' $OUTPUT/f16_mul_rne.tv +sed -ie 's/$/_1_2_4/' $OUTPUT/f16_mul_rz.tv +sed -ie 's/$/_3_2_4/' $OUTPUT/f16_mul_ru.tv +sed -ie 's/$/_2_2_4/' $OUTPUT/f16_mul_rd.tv +sed -ie 's/$/_4_2_4/' $OUTPUT/f16_mul_rnm.tv +echo "Editing f32_mul test vectors" +sed -ie 's/$/_0_0_4/' $OUTPUT/f32_mul_rne.tv +sed -ie 's/$/_1_0_4/' $OUTPUT/f32_mul_rz.tv +sed -ie 's/$/_3_0_4/' $OUTPUT/f32_mul_ru.tv +sed -ie 's/$/_2_0_4/' $OUTPUT/f32_mul_rd.tv +sed -ie 's/$/_4_0_4/' $OUTPUT/f32_mul_rnm.tv +echo "Editing f64_mul test vectors" +sed -ie 's/$/_0_1_4/' $OUTPUT/f64_mul_rne.tv +sed -ie 's/$/_1_1_4/' $OUTPUT/f64_mul_rz.tv +sed -ie 's/$/_3_1_4/' $OUTPUT/f64_mul_ru.tv +sed -ie 's/$/_2_1_4/' $OUTPUT/f64_mul_rd.tv +sed -ie 's/$/_4_1_4/' $OUTPUT/f64_mul_rnm.tv +echo "Editing f128_mul test vectors" +sed -ie 's/$/_0_3_4/' $OUTPUT/f128_mul_rne.tv +sed -ie 's/$/_1_3_4/' $OUTPUT/f128_mul_rz.tv +sed -ie 's/$/_3_3_4/' $OUTPUT/f128_mul_ru.tv +sed -ie 's/$/_2_3_4/' $OUTPUT/f128_mul_rd.tv +sed -ie 's/$/_4_3_4/' $OUTPUT/f128_mul_rnm.tv +echo "Editing f16_div test vectors" +sed -ie 's/$/_0_2_0/' $OUTPUT/f16_div_rne.tv +sed -ie 's/$/_1_2_0/' $OUTPUT/f16_div_rz.tv +sed -ie 's/$/_3_2_0/' $OUTPUT/f16_div_ru.tv +sed -ie 's/$/_2_2_0/' $OUTPUT/f16_div_rd.tv +sed -ie 's/$/_4_2_0/' $OUTPUT/f16_div_rnm.tv +echo "Editing f32_div test vectors" +sed -ie 's/$/_0_0_0/' $OUTPUT/f32_div_rne.tv +sed -ie 's/$/_1_0_0/' $OUTPUT/f32_div_rz.tv +sed -ie 's/$/_3_0_0/' $OUTPUT/f32_div_ru.tv +sed -ie 's/$/_2_0_0/' $OUTPUT/f32_div_rd.tv +sed -ie 's/$/_4_0_0/' $OUTPUT/f32_div_rnm.tv +echo "Editing f64_div test vectors" +sed -ie 's/$/_0_1_0/' $OUTPUT/f64_div_rne.tv +sed -ie 's/$/_1_1_0/' $OUTPUT/f64_div_rz.tv +sed -ie 's/$/_3_1_0/' $OUTPUT/f64_div_ru.tv +sed -ie 's/$/_2_1_0/' $OUTPUT/f64_div_rd.tv +sed -ie 's/$/_4_1_0/' $OUTPUT/f64_div_rnm.tv +echo "Editing f128_div test vectors" +sed -ie 's/$/_0_3_0/' $OUTPUT/f128_div_rne.tv +sed -ie 's/$/_1_3_0/' $OUTPUT/f128_div_rz.tv +sed -ie 's/$/_3_3_0/' $OUTPUT/f128_div_ru.tv +sed -ie 's/$/_2_3_0/' $OUTPUT/f128_div_rd.tv +sed -ie 's/$/_4_3_0/' $OUTPUT/f128_div_rnm.tv +echo "Editing f16_sqrt test vectors" +sed -ie 's/$/_0_2_1/' $OUTPUT/f16_sqrt_rne.tv +sed -ie 's/$/_1_2_1/' $OUTPUT/f16_sqrt_rz.tv +sed -ie 's/$/_3_2_1/' $OUTPUT/f16_sqrt_ru.tv +sed -ie 's/$/_2_2_1/' $OUTPUT/f16_sqrt_rd.tv +sed -ie 's/$/_4_2_1/' $OUTPUT/f16_sqrt_rnm.tv +echo "Editing f32_sqrt test vectors" +sed -ie 's/$/_0_0_1/' $OUTPUT/f32_sqrt_rne.tv +sed -ie 's/$/_1_0_1/' $OUTPUT/f32_sqrt_rz.tv +sed -ie 's/$/_3_0_1/' $OUTPUT/f32_sqrt_ru.tv +sed -ie 's/$/_2_0_1/' $OUTPUT/f32_sqrt_rd.tv +sed -ie 's/$/_4_0_1/' $OUTPUT/f32_sqrt_rnm.tv +echo "Editing f64_sqrt test vectors" +sed -ie 's/$/_0_1_1/' $OUTPUT/f64_sqrt_rne.tv +sed -ie 's/$/_1_1_1/' $OUTPUT/f64_sqrt_rz.tv +sed -ie 's/$/_3_1_1/' $OUTPUT/f64_sqrt_ru.tv +sed -ie 's/$/_2_1_1/' $OUTPUT/f64_sqrt_rd.tv +sed -ie 's/$/_4_1_1/' $OUTPUT/f64_sqrt_rnm.tv +echo "Editing f128_sqrt test vectors" +sed -ie 's/$/_0_3_1/' $OUTPUT/f128_sqrt_rne.tv +sed -ie 's/$/_1_3_1/' $OUTPUT/f128_sqrt_rz.tv +sed -ie 's/$/_3_3_1/' $OUTPUT/f128_sqrt_ru.tv +sed -ie 's/$/_2_3_1/' $OUTPUT/f128_sqrt_rd.tv +sed -ie 's/$/_4_3_1/' $OUTPUT/f128_sqrt_rnm.tv +echo "Editing f16_eq test vectors" +sed -ie 's/$/_0_2_2/' $OUTPUT/f16_eq_rne.tv +sed -ie 's/$/_1_2_2/' $OUTPUT/f16_eq_rz.tv +sed -ie 's/$/_3_2_2/' $OUTPUT/f16_eq_ru.tv +sed -ie 's/$/_2_2_2/' $OUTPUT/f16_eq_rd.tv +sed -ie 's/$/_4_2_2/' $OUTPUT/f16_eq_rnm.tv +echo "Editing f32_eq test vectors" +sed -ie 's/$/_0_0_2/' $OUTPUT/f32_eq_rne.tv +sed -ie 's/$/_1_0_2/' $OUTPUT/f32_eq_rz.tv +sed -ie 's/$/_3_0_2/' $OUTPUT/f32_eq_ru.tv +sed -ie 's/$/_2_0_2/' $OUTPUT/f32_eq_rd.tv +sed -ie 's/$/_4_0_2/' $OUTPUT/f32_eq_rnm.tv +echo "Editing f64_eq test vectors" +sed -ie 's/$/_0_1_2/' $OUTPUT/f64_eq_rne.tv +sed -ie 's/$/_1_1_2/' $OUTPUT/f64_eq_rz.tv +sed -ie 's/$/_3_1_2/' $OUTPUT/f64_eq_ru.tv +sed -ie 's/$/_2_1_2/' $OUTPUT/f64_eq_rd.tv +sed -ie 's/$/_4_1_2/' $OUTPUT/f64_eq_rnm.tv +echo "Editing f128_eq test vectors" +sed -ie 's/$/_0_3_2/' $OUTPUT/f128_eq_rne.tv +sed -ie 's/$/_1_3_2/' $OUTPUT/f128_eq_rz.tv +sed -ie 's/$/_3_3_2/' $OUTPUT/f128_eq_ru.tv +sed -ie 's/$/_2_3_2/' $OUTPUT/f128_eq_rd.tv +sed -ie 's/$/_4_3_2/' $OUTPUT/f128_eq_rnm.tv +echo "Editing f16_le test vectors" +sed -ie 's/$/_0_2_3/' $OUTPUT/f16_le_rne.tv +sed -ie 's/$/_1_2_3/' $OUTPUT/f16_le_rz.tv +sed -ie 's/$/_3_2_3/' $OUTPUT/f16_le_ru.tv +sed -ie 's/$/_2_2_3/' $OUTPUT/f16_le_rd.tv +sed -ie 's/$/_4_2_3/' $OUTPUT/f16_le_rnm.tv +echo "Editing f32_le test vectors" +sed -ie 's/$/_0_0_3/' $OUTPUT/f32_le_rne.tv +sed -ie 's/$/_1_0_3/' $OUTPUT/f32_le_rz.tv +sed -ie 's/$/_3_0_3/' $OUTPUT/f32_le_ru.tv +sed -ie 's/$/_2_0_3/' $OUTPUT/f32_le_rd.tv +sed -ie 's/$/_4_0_3/' $OUTPUT/f32_le_rnm.tv +echo "Editing f64_le test vectors" +sed -ie 's/$/_0_1_3/' $OUTPUT/f64_le_rne.tv +sed -ie 's/$/_1_1_3/' $OUTPUT/f64_le_rz.tv +sed -ie 's/$/_3_1_3/' $OUTPUT/f64_le_ru.tv +sed -ie 's/$/_2_1_3/' $OUTPUT/f64_le_rd.tv +sed -ie 's/$/_4_1_3/' $OUTPUT/f64_le_rnm.tv +echo "Editing f128_le test vectors" +sed -ie 's/$/_0_3_3/' $OUTPUT/f128_le_rne.tv +sed -ie 's/$/_1_3_3/' $OUTPUT/f128_le_rz.tv +sed -ie 's/$/_3_3_3/' $OUTPUT/f128_le_ru.tv +sed -ie 's/$/_2_3_3/' $OUTPUT/f128_le_rd.tv +sed -ie 's/$/_4_3_3/' $OUTPUT/f128_le_rnm.tv +echo "Editing f16_lt test vectors" +sed -ie 's/$/_0_2_1/' $OUTPUT/f16_lt_rne.tv +sed -ie 's/$/_1_2_1/' $OUTPUT/f16_lt_rz.tv +sed -ie 's/$/_3_2_1/' $OUTPUT/f16_lt_ru.tv +sed -ie 's/$/_2_2_1/' $OUTPUT/f16_lt_rd.tv +sed -ie 's/$/_4_2_1/' $OUTPUT/f16_lt_rnm.tv +echo "Editing f32_lt test vectors" +sed -ie 's/$/_0_0_1/' $OUTPUT/f32_lt_rne.tv +sed -ie 's/$/_1_0_1/' $OUTPUT/f32_lt_rz.tv +sed -ie 's/$/_3_0_1/' $OUTPUT/f32_lt_ru.tv +sed -ie 's/$/_2_0_1/' $OUTPUT/f32_lt_rd.tv +sed -ie 's/$/_4_0_1/' $OUTPUT/f32_lt_rnm.tv +echo "Editing f64_lt test vectors" +sed -ie 's/$/_0_1_1/' $OUTPUT/f64_lt_rne.tv +sed -ie 's/$/_1_1_1/' $OUTPUT/f64_lt_rz.tv +sed -ie 's/$/_3_1_1/' $OUTPUT/f64_lt_ru.tv +sed -ie 's/$/_2_1_1/' $OUTPUT/f64_lt_rd.tv +sed -ie 's/$/_4_1_1/' $OUTPUT/f64_lt_rnm.tv +echo "Editing f128_lt test vectors" +sed -ie 's/$/_0_3_1/' $OUTPUT/f128_lt_rne.tv +sed -ie 's/$/_1_3_1/' $OUTPUT/f128_lt_rz.tv +sed -ie 's/$/_3_3_1/' $OUTPUT/f128_lt_ru.tv +sed -ie 's/$/_2_3_1/' $OUTPUT/f128_lt_rd.tv +sed -ie 's/$/_4_3_1/' $OUTPUT/f128_lt_rnm.tv +echo "Editing f16_mulAdd test vectors" +sed -ie 's/$/_0_2_0/' $OUTPUT/f16_mulAdd_rne.tv +sed -ie 's/$/_1_2_0/' $OUTPUT/f16_mulAdd_rz.tv +sed -ie 's/$/_3_2_0/' $OUTPUT/f16_mulAdd_ru.tv +sed -ie 's/$/_2_2_0/' $OUTPUT/f16_mulAdd_rd.tv +sed -ie 's/$/_4_2_0/' $OUTPUT/f16_mulAdd_rnm.tv +echo "Editing f32_mulAdd test vectors" +sed -ie 's/$/_0_0_0/' $OUTPUT/f32_mulAdd_rne.tv +sed -ie 's/$/_1_0_0/' $OUTPUT/f32_mulAdd_rz.tv +sed -ie 's/$/_3_0_0/' $OUTPUT/f32_mulAdd_ru.tv +sed -ie 's/$/_2_0_0/' $OUTPUT/f32_mulAdd_rd.tv +sed -ie 's/$/_4_0_0/' $OUTPUT/f32_mulAdd_rnm.tv +echo "Editing f64_mulAdd test vectors" +sed -ie 's/$/_0_1_0/' $OUTPUT/f64_mulAdd_rne.tv +sed -ie 's/$/_1_1_0/' $OUTPUT/f64_mulAdd_rz.tv +sed -ie 's/$/_3_1_0/' $OUTPUT/f64_mulAdd_ru.tv +sed -ie 's/$/_2_1_0/' $OUTPUT/f64_mulAdd_rd.tv +sed -ie 's/$/_4_1_0/' $OUTPUT/f64_mulAdd_rnm.tv +echo "Editing f128_mulAdd test vectors" +sed -ie 's/$/_0_3_0/' $OUTPUT/f128_mulAdd_rne.tv +sed -ie 's/$/_1_3_0/' $OUTPUT/f128_mulAdd_rz.tv +sed -ie 's/$/_3_3_0/' $OUTPUT/f128_mulAdd_ru.tv +sed -ie 's/$/_2_3_0/' $OUTPUT/f128_mulAdd_rd.tv +sed -ie 's/$/_4_3_0/' $OUTPUT/f128_mulAdd_rnm.tv +rm vectors/*.tve \ No newline at end of file diff --git a/tests/fp/create_vectors.sh b/tests/fp/create_vectors.sh new file mode 100755 index 00000000..bac71c60 --- /dev/null +++ b/tests/fp/create_vectors.sh @@ -0,0 +1,483 @@ +#!/bin/sh +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" +OUTPUT="./vectors" +echo "Creating ui32_to_f16 convert vectors" +$BUILD/testfloat_gen -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv +$BUILD/testfloat_gen -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv +$BUILD/testfloat_gen -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv +$BUILD/testfloat_gen -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv +$BUILD/testfloat_gen -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv +echo "Creating ui32_to_f32 convert vectors" +$BUILD/testfloat_gen -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv +$BUILD/testfloat_gen -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv +$BUILD/testfloat_gen -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv +$BUILD/testfloat_gen -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv +echo "Creating ui32_to_f64 convert vectors" +$BUILD/testfloat_gen -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv +$BUILD/testfloat_gen -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv +$BUILD/testfloat_gen -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv +$BUILD/testfloat_gen -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv +echo "Creating ui32_to_f128 convert vectors" +$BUILD/testfloat_gen -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv +$BUILD/testfloat_gen -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv +$BUILD/testfloat_gen -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv +$BUILD/testfloat_gen -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv +$BUILD/testfloat_gen -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv +echo "Creating ui64_to_f16 convert vectors" +$BUILD/testfloat_gen -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv +$BUILD/testfloat_gen -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv +$BUILD/testfloat_gen -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv +$BUILD/testfloat_gen -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv +$BUILD/testfloat_gen -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv +echo "Creating ui64_to_f32 convert vectors" +$BUILD/testfloat_gen -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv +$BUILD/testfloat_gen -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv +$BUILD/testfloat_gen -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv +$BUILD/testfloat_gen -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv +echo "Creating ui64_to_f64 convert vectors" +$BUILD/testfloat_gen -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv +$BUILD/testfloat_gen -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv +$BUILD/testfloat_gen -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv +$BUILD/testfloat_gen -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv +echo "Creating ui64_to_f128 convert vectors" +$BUILD/testfloat_gen -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv +$BUILD/testfloat_gen -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv +$BUILD/testfloat_gen -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv +$BUILD/testfloat_gen -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv +$BUILD/testfloat_gen -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv +echo "Creating i32_to_f16 convert vectors" +$BUILD/testfloat_gen -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv +$BUILD/testfloat_gen -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv +$BUILD/testfloat_gen -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv +$BUILD/testfloat_gen -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv +$BUILD/testfloat_gen -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv +echo "Creating i32_to_f32 convert vectors" +$BUILD/testfloat_gen -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv +$BUILD/testfloat_gen -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv +$BUILD/testfloat_gen -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv +$BUILD/testfloat_gen -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv +echo "Creating i32_to_f64 convert vectors" +$BUILD/testfloat_gen -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv +$BUILD/testfloat_gen -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv +$BUILD/testfloat_gen -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv +$BUILD/testfloat_gen -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv +echo "Creating i32_to_f128 convert vectors" +$BUILD/testfloat_gen -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv +$BUILD/testfloat_gen -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv +$BUILD/testfloat_gen -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv +$BUILD/testfloat_gen -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv +$BUILD/testfloat_gen -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv +echo "Creating i64_to_f16 convert vectors" +$BUILD/testfloat_gen -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv +$BUILD/testfloat_gen -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv +$BUILD/testfloat_gen -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv +$BUILD/testfloat_gen -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv +$BUILD/testfloat_gen -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv +echo "Creating i64_to_f32 convert vectors" +$BUILD/testfloat_gen -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv +$BUILD/testfloat_gen -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv +$BUILD/testfloat_gen -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv +$BUILD/testfloat_gen -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv +echo "Creating i64_to_f64 convert vectors" +$BUILD/testfloat_gen -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv +$BUILD/testfloat_gen -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv +$BUILD/testfloat_gen -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv +$BUILD/testfloat_gen -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv +echo "Creating i64_to_f128 convert vectors" +$BUILD/testfloat_gen -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv +$BUILD/testfloat_gen -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv +$BUILD/testfloat_gen -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv +$BUILD/testfloat_gen -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv +$BUILD/testfloat_gen -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv +echo "Creating f16_to_ui32 convert vectors" +$BUILD/testfloat_gen -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv +$BUILD/testfloat_gen -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv +$BUILD/testfloat_gen -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv +$BUILD/testfloat_gen -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv +echo "Creating f32_to_ui32 convert vectors" +$BUILD/testfloat_gen -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv +$BUILD/testfloat_gen -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv +$BUILD/testfloat_gen -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv +$BUILD/testfloat_gen -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv +echo "Creating f64_to_ui32 convert vectors" +$BUILD/testfloat_gen -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv +$BUILD/testfloat_gen -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv +$BUILD/testfloat_gen -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv +$BUILD/testfloat_gen -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv +echo "Creating f128_to_ui32 convert vectors" +$BUILD/testfloat_gen -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv +$BUILD/testfloat_gen -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv +$BUILD/testfloat_gen -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv +$BUILD/testfloat_gen -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv +echo "Creating f16_to_ui64 convert vectors" +$BUILD/testfloat_gen -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv +$BUILD/testfloat_gen -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv +$BUILD/testfloat_gen -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv +$BUILD/testfloat_gen -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv +echo "Creating f32_to_ui64 convert vectors" +$BUILD/testfloat_gen -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv +$BUILD/testfloat_gen -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv +$BUILD/testfloat_gen -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv +$BUILD/testfloat_gen -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv +echo "Creating f64_to_ui64 convert vectors" +$BUILD/testfloat_gen -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv +$BUILD/testfloat_gen -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv +$BUILD/testfloat_gen -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv +$BUILD/testfloat_gen -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv +echo "Creating f128_to_ui64 convert vectors" +$BUILD/testfloat_gen -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv +$BUILD/testfloat_gen -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv +$BUILD/testfloat_gen -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv +$BUILD/testfloat_gen -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv +echo "Creating f16_to_i32 convert vectors" +$BUILD/testfloat_gen -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv +$BUILD/testfloat_gen -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv +$BUILD/testfloat_gen -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv +$BUILD/testfloat_gen -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv +echo "Creating f32_to_i32 convert vectors" +$BUILD/testfloat_gen -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv +$BUILD/testfloat_gen -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv +$BUILD/testfloat_gen -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv +$BUILD/testfloat_gen -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv +echo "Creating f64_to_i32 convert vectors" +$BUILD/testfloat_gen -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv +$BUILD/testfloat_gen -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv +$BUILD/testfloat_gen -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv +$BUILD/testfloat_gen -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv +echo "Creating f128_to_i32 convert vectors" +$BUILD/testfloat_gen -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv +$BUILD/testfloat_gen -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv +$BUILD/testfloat_gen -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv +$BUILD/testfloat_gen -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv +echo "Creating f16_to_i64 convert vectors" +$BUILD/testfloat_gen -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv +$BUILD/testfloat_gen -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv +$BUILD/testfloat_gen -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv +$BUILD/testfloat_gen -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv +echo "Creating f32_to_i64 convert vectors" +$BUILD/testfloat_gen -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv +$BUILD/testfloat_gen -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv +$BUILD/testfloat_gen -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv +$BUILD/testfloat_gen -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv +echo "Creating f64_to_i64 convert vectors" +$BUILD/testfloat_gen -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv +$BUILD/testfloat_gen -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv +$BUILD/testfloat_gen -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv +$BUILD/testfloat_gen -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv +echo "Creating f128_to_i64 convert vectors" +$BUILD/testfloat_gen -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv +$BUILD/testfloat_gen -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv +$BUILD/testfloat_gen -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv +$BUILD/testfloat_gen -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv +echo "Creating f16_to_f32 convert vectors" +$BUILD/testfloat_gen -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv +$BUILD/testfloat_gen -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv +$BUILD/testfloat_gen -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv +$BUILD/testfloat_gen -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv +echo "Creating f16_to_f64 convert vectors" +$BUILD/testfloat_gen -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv +$BUILD/testfloat_gen -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv +$BUILD/testfloat_gen -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv +$BUILD/testfloat_gen -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv +echo "Creating f16_to_f128 convert vectors" +$BUILD/testfloat_gen -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv +$BUILD/testfloat_gen -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv +$BUILD/testfloat_gen -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv +$BUILD/testfloat_gen -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv +echo "Creating f32_to_f16 convert vectors" +$BUILD/testfloat_gen -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv +$BUILD/testfloat_gen -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv +$BUILD/testfloat_gen -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv +$BUILD/testfloat_gen -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv +echo "Creating f32_to_f64 convert vectors" +$BUILD/testfloat_gen -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv +$BUILD/testfloat_gen -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv +$BUILD/testfloat_gen -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv +$BUILD/testfloat_gen -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv +echo "Creating f32_to_f128 convert vectors" +$BUILD/testfloat_gen -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv +$BUILD/testfloat_gen -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv +$BUILD/testfloat_gen -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv +$BUILD/testfloat_gen -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv +echo "Creating f64_to_f16 convert vectors" +$BUILD/testfloat_gen -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv +$BUILD/testfloat_gen -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv +$BUILD/testfloat_gen -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv +$BUILD/testfloat_gen -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv +echo "Creating f64_to_f32 convert vectors" +$BUILD/testfloat_gen -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv +$BUILD/testfloat_gen -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv +$BUILD/testfloat_gen -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv +$BUILD/testfloat_gen -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv +echo "Creating f64_to_f128 convert vectors" +$BUILD/testfloat_gen -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv +$BUILD/testfloat_gen -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv +$BUILD/testfloat_gen -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv +$BUILD/testfloat_gen -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv +echo "Creating f128_to_f16 convert vectors" +$BUILD/testfloat_gen -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv +$BUILD/testfloat_gen -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv +$BUILD/testfloat_gen -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv +$BUILD/testfloat_gen -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv +echo "Creating f128_to_f32 convert vectors" +$BUILD/testfloat_gen -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv +$BUILD/testfloat_gen -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv +$BUILD/testfloat_gen -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv +$BUILD/testfloat_gen -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv +echo "Creating f128_to_f64 convert vectors" +$BUILD/testfloat_gen -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv +$BUILD/testfloat_gen -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv +$BUILD/testfloat_gen -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv +$BUILD/testfloat_gen -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv +echo "Creating f16_add vectors" +$BUILD/testfloat_gen -rnear_even f16_add > $OUTPUT/f16_add_rne.tv +$BUILD/testfloat_gen -rminMag f16_add > $OUTPUT/f16_add_rz.tv +$BUILD/testfloat_gen -rmax f16_add > $OUTPUT/f16_add_ru.tv +$BUILD/testfloat_gen -rmin f16_add > $OUTPUT/f16_add_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv +echo "Creating f32_add vectors" +$BUILD/testfloat_gen -rnear_even f32_add > $OUTPUT/f32_add_rne.tv +$BUILD/testfloat_gen -rminMag f32_add > $OUTPUT/f32_add_rz.tv +$BUILD/testfloat_gen -rmax f32_add > $OUTPUT/f32_add_ru.tv +$BUILD/testfloat_gen -rmin f32_add > $OUTPUT/f32_add_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv +echo "Creating f64_add vectors" +$BUILD/testfloat_gen -rnear_even f64_add > $OUTPUT/f64_add_rne.tv +$BUILD/testfloat_gen -rminMag f64_add > $OUTPUT/f64_add_rz.tv +$BUILD/testfloat_gen -rmax f64_add > $OUTPUT/f64_add_ru.tv +$BUILD/testfloat_gen -rmin f64_add > $OUTPUT/f64_add_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv +echo "Creating f128_add vectors" +$BUILD/testfloat_gen -rnear_even f128_add > $OUTPUT/f128_add_rne.tv +$BUILD/testfloat_gen -rminMag f128_add > $OUTPUT/f128_add_rz.tv +$BUILD/testfloat_gen -rmax f128_add > $OUTPUT/f128_add_ru.tv +$BUILD/testfloat_gen -rmin f128_add > $OUTPUT/f128_add_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv +echo "Creating f16_sub vectors" +$BUILD/testfloat_gen -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv +$BUILD/testfloat_gen -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv +$BUILD/testfloat_gen -rmax f16_sub > $OUTPUT/f16_sub_ru.tv +$BUILD/testfloat_gen -rmin f16_sub > $OUTPUT/f16_sub_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv +echo "Creating f32_sub vectors" +$BUILD/testfloat_gen -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv +$BUILD/testfloat_gen -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv +$BUILD/testfloat_gen -rmax f32_sub > $OUTPUT/f32_sub_ru.tv +$BUILD/testfloat_gen -rmin f32_sub > $OUTPUT/f32_sub_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv +echo "Creating f64_sub vectors" +$BUILD/testfloat_gen -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv +$BUILD/testfloat_gen -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv +$BUILD/testfloat_gen -rmax f64_sub > $OUTPUT/f64_sub_ru.tv +$BUILD/testfloat_gen -rmin f64_sub > $OUTPUT/f64_sub_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv +echo "Creating f128_sub vectors" +$BUILD/testfloat_gen -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv +$BUILD/testfloat_gen -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv +$BUILD/testfloat_gen -rmax f128_sub > $OUTPUT/f128_sub_ru.tv +$BUILD/testfloat_gen -rmin f128_sub > $OUTPUT/f128_sub_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv +echo "Creating f16_mul vectors" +$BUILD/testfloat_gen -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv +$BUILD/testfloat_gen -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv +$BUILD/testfloat_gen -rmax f16_mul > $OUTPUT/f16_mul_ru.tv +$BUILD/testfloat_gen -rmin f16_mul > $OUTPUT/f16_mul_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv +echo "Creating f32_mul vectors" +$BUILD/testfloat_gen -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv +$BUILD/testfloat_gen -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv +$BUILD/testfloat_gen -rmax f32_mul > $OUTPUT/f32_mul_ru.tv +$BUILD/testfloat_gen -rmin f32_mul > $OUTPUT/f32_mul_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv +echo "Creating f64_mul vectors" +$BUILD/testfloat_gen -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv +$BUILD/testfloat_gen -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv +$BUILD/testfloat_gen -rmax f64_mul > $OUTPUT/f64_mul_ru.tv +$BUILD/testfloat_gen -rmin f64_mul > $OUTPUT/f64_mul_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv +echo "Creating f128_mul vectors" +$BUILD/testfloat_gen -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv +$BUILD/testfloat_gen -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv +$BUILD/testfloat_gen -rmax f128_mul > $OUTPUT/f128_mul_ru.tv +$BUILD/testfloat_gen -rmin f128_mul > $OUTPUT/f128_mul_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv +echo "Creating f16_div vectors" +$BUILD/testfloat_gen -rnear_even f16_div > $OUTPUT/f16_div_rne.tv +$BUILD/testfloat_gen -rminMag f16_div > $OUTPUT/f16_div_rz.tv +$BUILD/testfloat_gen -rmax f16_div > $OUTPUT/f16_div_ru.tv +$BUILD/testfloat_gen -rmin f16_div > $OUTPUT/f16_div_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv +echo "Creating f32_div vectors" +$BUILD/testfloat_gen -rnear_even f32_div > $OUTPUT/f32_div_rne.tv +$BUILD/testfloat_gen -rminMag f32_div > $OUTPUT/f32_div_rz.tv +$BUILD/testfloat_gen -rmax f32_div > $OUTPUT/f32_div_ru.tv +$BUILD/testfloat_gen -rmin f32_div > $OUTPUT/f32_div_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv +echo "Creating f64_div vectors" +$BUILD/testfloat_gen -rnear_even f64_div > $OUTPUT/f64_div_rne.tv +$BUILD/testfloat_gen -rminMag f64_div > $OUTPUT/f64_div_rz.tv +$BUILD/testfloat_gen -rmax f64_div > $OUTPUT/f64_div_ru.tv +$BUILD/testfloat_gen -rmin f64_div > $OUTPUT/f64_div_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv +echo "Creating f128_div vectors" +$BUILD/testfloat_gen -rnear_even f128_div > $OUTPUT/f128_div_rne.tv +$BUILD/testfloat_gen -rminMag f128_div > $OUTPUT/f128_div_rz.tv +$BUILD/testfloat_gen -rmax f128_div > $OUTPUT/f128_div_ru.tv +$BUILD/testfloat_gen -rmin f128_div > $OUTPUT/f128_div_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv +echo "Creating f16_sqrt vectors" +$BUILD/testfloat_gen -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv +$BUILD/testfloat_gen -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv +$BUILD/testfloat_gen -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv +$BUILD/testfloat_gen -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv +echo "Creating f32_sqrt vectors" +$BUILD/testfloat_gen -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv +$BUILD/testfloat_gen -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv +$BUILD/testfloat_gen -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv +$BUILD/testfloat_gen -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv +echo "Creating f64_sqrt vectors" +$BUILD/testfloat_gen -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv +$BUILD/testfloat_gen -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv +$BUILD/testfloat_gen -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv +$BUILD/testfloat_gen -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv +echo "Creating f128_sqrt vectors" +$BUILD/testfloat_gen -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv +$BUILD/testfloat_gen -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv +$BUILD/testfloat_gen -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv +$BUILD/testfloat_gen -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv +echo "Creating f16_eq vectors" +$BUILD/testfloat_gen -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv +$BUILD/testfloat_gen -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv +$BUILD/testfloat_gen -rmax f16_eq > $OUTPUT/f16_eq_ru.tv +$BUILD/testfloat_gen -rmin f16_eq > $OUTPUT/f16_eq_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv +echo "Creating f32_eq vectors" +$BUILD/testfloat_gen -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv +$BUILD/testfloat_gen -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv +$BUILD/testfloat_gen -rmax f32_eq > $OUTPUT/f32_eq_ru.tv +$BUILD/testfloat_gen -rmin f32_eq > $OUTPUT/f32_eq_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv +echo "Creating f64_eq vectors" +$BUILD/testfloat_gen -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv +$BUILD/testfloat_gen -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv +$BUILD/testfloat_gen -rmax f64_eq > $OUTPUT/f64_eq_ru.tv +$BUILD/testfloat_gen -rmin f64_eq > $OUTPUT/f64_eq_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv +echo "Creating f128_eq vectors" +$BUILD/testfloat_gen -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv +$BUILD/testfloat_gen -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv +$BUILD/testfloat_gen -rmax f128_eq > $OUTPUT/f128_eq_ru.tv +$BUILD/testfloat_gen -rmin f128_eq > $OUTPUT/f128_eq_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv +echo "Creating f16_le vectors" +$BUILD/testfloat_gen -rnear_even f16_le > $OUTPUT/f16_le_rne.tv +$BUILD/testfloat_gen -rminMag f16_le > $OUTPUT/f16_le_rz.tv +$BUILD/testfloat_gen -rmax f16_le > $OUTPUT/f16_le_ru.tv +$BUILD/testfloat_gen -rmin f16_le > $OUTPUT/f16_le_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv +echo "Creating f32_le vectors" +$BUILD/testfloat_gen -rnear_even f32_le > $OUTPUT/f32_le_rne.tv +$BUILD/testfloat_gen -rminMag f32_le > $OUTPUT/f32_le_rz.tv +$BUILD/testfloat_gen -rmax f32_le > $OUTPUT/f32_le_ru.tv +$BUILD/testfloat_gen -rmin f32_le > $OUTPUT/f32_le_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv +echo "Creating f64_le vectors" +$BUILD/testfloat_gen -rnear_even f64_le > $OUTPUT/f64_le_rne.tv +$BUILD/testfloat_gen -rminMag f64_le > $OUTPUT/f64_le_rz.tv +$BUILD/testfloat_gen -rmax f64_le > $OUTPUT/f64_le_ru.tv +$BUILD/testfloat_gen -rmin f64_le > $OUTPUT/f64_le_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv +echo "Creating f128_le vectors" +$BUILD/testfloat_gen -rnear_even f128_le > $OUTPUT/f128_le_rne.tv +$BUILD/testfloat_gen -rminMag f128_le > $OUTPUT/f128_le_rz.tv +$BUILD/testfloat_gen -rmax f128_le > $OUTPUT/f128_le_ru.tv +$BUILD/testfloat_gen -rmin f128_le > $OUTPUT/f128_le_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv +echo "Creating f16_lt vectors" +$BUILD/testfloat_gen -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv +$BUILD/testfloat_gen -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv +$BUILD/testfloat_gen -rmax f16_lt > $OUTPUT/f16_lt_ru.tv +$BUILD/testfloat_gen -rmin f16_lt > $OUTPUT/f16_lt_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv +echo "Creating f32_lt vectors" +$BUILD/testfloat_gen -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv +$BUILD/testfloat_gen -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv +$BUILD/testfloat_gen -rmax f32_lt > $OUTPUT/f32_lt_ru.tv +$BUILD/testfloat_gen -rmin f32_lt > $OUTPUT/f32_lt_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv +echo "Creating f64_lt vectors" +$BUILD/testfloat_gen -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv +$BUILD/testfloat_gen -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv +$BUILD/testfloat_gen -rmax f64_lt > $OUTPUT/f64_lt_ru.tv +$BUILD/testfloat_gen -rmin f64_lt > $OUTPUT/f64_lt_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv +echo "Creating f128_lt vectors" +$BUILD/testfloat_gen -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv +$BUILD/testfloat_gen -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv +$BUILD/testfloat_gen -rmax f128_lt > $OUTPUT/f128_lt_ru.tv +$BUILD/testfloat_gen -rmin f128_lt > $OUTPUT/f128_lt_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv +echo "Creating f16_mulAdd vectors" +$BUILD/testfloat_gen -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv +$BUILD/testfloat_gen -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv +$BUILD/testfloat_gen -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv +$BUILD/testfloat_gen -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv +echo "Creating f32_mulAdd vectors" +$BUILD/testfloat_gen -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv +$BUILD/testfloat_gen -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv +$BUILD/testfloat_gen -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv +$BUILD/testfloat_gen -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv +echo "Creating f64_mulAdd vectors" +$BUILD/testfloat_gen -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv +$BUILD/testfloat_gen -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv +$BUILD/testfloat_gen -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv +$BUILD/testfloat_gen -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv +echo "Creating f128_mulAdd vectors" +$BUILD/testfloat_gen -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv +$BUILD/testfloat_gen -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv +$BUILD/testfloat_gen -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv +$BUILD/testfloat_gen -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv diff --git a/tests/fp/create_vectors128fma.sh b/tests/fp/create_vectors128fma.sh deleted file mode 100755 index 361a4add..00000000 --- a/tests/fp/create_vectors128fma.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh - -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv -$BUILD/testfloat_gen -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv -$BUILD/testfloat_gen -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv -$BUILD/testfloat_gen -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv - -# format: X_Y_Z_answer_flags_Frm_Fmt -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv -sed -ie 's/$/_0/' $OUTPUT/f128_mulAdd_rne.tv -sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rne.tv - -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv -sed -ie 's/$/_1/' $OUTPUT/f128_mulAdd_rz.tv -sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rz.tv - -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv -sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_ru.tv -sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_ru.tv - -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv -sed -ie 's/$/_2/' $OUTPUT/f128_mulAdd_rd.tv -sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rd.tv - -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv -sed -ie 's/$/_4/' $OUTPUT/f128_mulAdd_rnm.tv -sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rnm.tv \ No newline at end of file diff --git a/tests/fp/create_vectors16.sh b/tests/fp/create_vectors16.sh deleted file mode 100755 index 85bfacaa..00000000 --- a/tests/fp/create_vectors16.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh - -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f16_add > $OUTPUT/f16_add_rne.tv -$BUILD/testfloat_gen -rminMag f16_add > $OUTPUT/f16_add_rz.tv -$BUILD/testfloat_gen -rmin f16_add > $OUTPUT/f16_add_ru.tv -$BUILD/testfloat_gen -rmax f16_add > $OUTPUT/f16_add_rd.tv - -$BUILD/testfloat_gen -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv -$BUILD/testfloat_gen -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv -$BUILD/testfloat_gen -rmin f16_sub > $OUTPUT/f16_sub_ru.tv -$BUILD/testfloat_gen -rmax f16_sub > $OUTPUT/f16_sub_rd.tv - -$BUILD/testfloat_gen -rnear_even f16_div > $OUTPUT/f16_div_rne.tv -$BUILD/testfloat_gen -rminMag f16_div > $OUTPUT/f16_div_rz.tv -$BUILD/testfloat_gen -rmin f16_div > $OUTPUT/f16_div_ru.tv -$BUILD/testfloat_gen -rmax f16_div > $OUTPUT/f16_div_rd.tv - -$BUILD/testfloat_gen -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv -$BUILD/testfloat_gen -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv -$BUILD/testfloat_gen -rmin f16_sqrt > $OUTPUT/f16_sqrt_ru.tv -$BUILD/testfloat_gen -rmax f16_sqrt > $OUTPUT/f16_sqrt_rd.tv - -$BUILD/testfloat_gen -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv -$BUILD/testfloat_gen -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv -$BUILD/testfloat_gen -rmax f16_mul > $OUTPUT/f16_mul_ru.tv -$BUILD/testfloat_gen -rmin f16_mul > $OUTPUT/f16_mul_rd.tv - - diff --git a/tests/fp/create_vectors16fma.sh b/tests/fp/create_vectors16fma.sh deleted file mode 100755 index d46e8768..00000000 --- a/tests/fp/create_vectors16fma.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh - -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv -$BUILD/testfloat_gen -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv -$BUILD/testfloat_gen -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv -$BUILD/testfloat_gen -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv - -# format: X_Y_Z_answer_flags_Frm_Fmt -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv -sed -ie 's/$/_0/' $OUTPUT/f16_mulAdd_rne.tv -sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rne.tv - -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv -sed -ie 's/$/_1/' $OUTPUT/f16_mulAdd_rz.tv -sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rz.tv - -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv -sed -ie 's/$/_3/' $OUTPUT/f16_mulAdd_ru.tv -sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_ru.tv - -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv -sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rd.tv -sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rd.tv - -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv -sed -ie 's/$/_4/' $OUTPUT/f16_mulAdd_rnm.tv -sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rnm.tv \ No newline at end of file diff --git a/tests/fp/create_vectors32.sh b/tests/fp/create_vectors32.sh deleted file mode 100755 index 003d8ee3..00000000 --- a/tests/fp/create_vectors32.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/sh - -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f32_add > $OUTPUT/f32_add_rne.tv -$BUILD/testfloat_gen -rminMag f32_add > $OUTPUT/f32_add_rz.tv -$BUILD/testfloat_gen -rmax f32_add > $OUTPUT/f32_add_ru.tv -$BUILD/testfloat_gen -rmin f32_add > $OUTPUT/f32_add_rd.tv - -$BUILD/testfloat_gen -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv -$BUILD/testfloat_gen -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv -$BUILD/testfloat_gen -rmax f32_sub > $OUTPUT/f32_sub_ru.tv -$BUILD/testfloat_gen -rmin f32_sub > $OUTPUT/f32_sub_rd.tv - -$BUILD/testfloat_gen -rnear_even f32_div > $OUTPUT/f32_div_rne.tv -$BUILD/testfloat_gen -rminMag f32_div > $OUTPUT/f32_div_rz.tv -$BUILD/testfloat_gen -rmax f32_div > $OUTPUT/f32_div_ru.tv -$BUILD/testfloat_gen -rmin f32_div > $OUTPUT/f32_div_rd.tv - -$BUILD/testfloat_gen -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv -$BUILD/testfloat_gen -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv -$BUILD/testfloat_gen -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv -$BUILD/testfloat_gen -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv - -$BUILD/testfloat_gen -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv -$BUILD/testfloat_gen -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv -$BUILD/testfloat_gen -rmax f32_mul > $OUTPUT/f32_mul_ru.tv -$BUILD/testfloat_gen -rmin f32_mul > $OUTPUT/f32_mul_rd.tv diff --git a/tests/fp/create_vectors32_64.sh b/tests/fp/create_vectors32_64.sh deleted file mode 100755 index be14f71d..00000000 --- a/tests/fp/create_vectors32_64.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh - -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f32_to_f64 > $OUTPUT/f32_f64_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_f64 > $OUTPUT/f32_f64_rz.tv -$BUILD/testfloat_gen -rmax f32_to_f64 > $OUTPUT/f32_f64_ru.tv -$BUILD/testfloat_gen -rmin f32_to_f64 > $OUTPUT/f32_f64_rd.tv - -$BUILD/testfloat_gen -rnear_even f32_to_i64 > $OUTPUT/f32_i64_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_i64 > $OUTPUT/f32_i64_rz.tv -$BUILD/testfloat_gen -rmax f32_to_i64 > $OUTPUT/f32_i64_ru.tv -$BUILD/testfloat_gen -rmin f32_to_i64 > $OUTPUT/f32_i64_rd.tv - -$BUILD/testfloat_gen -rnear_even f32_to_ui64 > $OUTPUT/f32_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_ui64 > $OUTPUT/f32_ui64_rz.tv -$BUILD/testfloat_gen -rmax f32_to_ui64 > $OUTPUT/f32_ui64_ru.tv -$BUILD/testfloat_gen -rmin f32_to_ui64 > $OUTPUT/f32_ui64_rd.tv - diff --git a/tests/fp/create_vectors32cmp.sh b/tests/fp/create_vectors32cmp.sh deleted file mode 100755 index eb4acec7..00000000 --- a/tests/fp/create_vectors32cmp.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen f32_eq > $OUTPUT/f32_cmp_eq.tv -$BUILD/testfloat_gen f32_le > $OUTPUT/f32_cmp_le.tv -$BUILD/testfloat_gen f32_lt > $OUTPUT/f32_cmp_lt.tv - -$BUILD/testfloat_gen f32_eq_signaling > $OUTPUT/f32_cmp_eq_signaling.tv -$BUILD/testfloat_gen f32_le_quiet > $OUTPUT/f32_cmp_le_quiet.tv -$BUILD/testfloat_gen f32_lt_quiet > $OUTPUT/f32_cmp_lt_quiet.tv - diff --git a/tests/fp/create_vectors32fma.sh b/tests/fp/create_vectors32fma.sh deleted file mode 100755 index 7e48d1ab..00000000 --- a/tests/fp/create_vectors32fma.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh - -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv -$BUILD/testfloat_gen -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv -$BUILD/testfloat_gen -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv -$BUILD/testfloat_gen -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv - -# format: X_Y_Z_answer_flags_Frm_Fmt -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv -sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rne.tv -sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rne.tv - -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv -sed -ie 's/$/_1/' $OUTPUT/f32_mulAdd_rz.tv -sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rz.tv - -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv -sed -ie 's/$/_3/' $OUTPUT/f32_mulAdd_ru.tv -sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_ru.tv - -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv -sed -ie 's/$/_2/' $OUTPUT/f32_mulAdd_rd.tv -sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rd.tv - -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv -sed -ie 's/$/_4/' $OUTPUT/f32_mulAdd_rnm.tv -sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rnm.tv \ No newline at end of file diff --git a/tests/fp/create_vectors64.sh b/tests/fp/create_vectors64.sh deleted file mode 100755 index b21d2c26..00000000 --- a/tests/fp/create_vectors64.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh - -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f64_add > $OUTPUT/f64_add_rne.tv -$BUILD/testfloat_gen -rminMag f64_add > $OUTPUT/f64_add_rz.tv -$BUILD/testfloat_gen -rmax f64_add > $OUTPUT/f64_add_ru.tv -$BUILD/testfloat_gen -rmin f64_add > $OUTPUT/f64_add_rd.tv - -$BUILD/testfloat_gen -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv -$BUILD/testfloat_gen -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv -$BUILD/testfloat_gen -rmax f64_sub > $OUTPUT/f64_sub_ru.tv -$BUILD/testfloat_gen -rmin f64_sub > $OUTPUT/f64_sub_rd.tv - -$BUILD/testfloat_gen -rnear_even f64_div > $OUTPUT/f64_div_rne.tv -$BUILD/testfloat_gen -rminMag f64_div > $OUTPUT/f64_div_rz.tv -$BUILD/testfloat_gen -rmax f64_div > $OUTPUT/f64_div_ru.tv -$BUILD/testfloat_gen -rmin f64_div > $OUTPUT/f64_div_rd.tv - -$BUILD/testfloat_gen -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv -$BUILD/testfloat_gen -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv -$BUILD/testfloat_gen -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv -$BUILD/testfloat_gen -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv - -$BUILD/testfloat_gen -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv -$BUILD/testfloat_gen -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv -$BUILD/testfloat_gen -rmax f64_mul > $OUTPUT/f64_mul_ru.tv -$BUILD/testfloat_gen -rmin f64_mul > $OUTPUT/f64_mul_rd.tv - diff --git a/tests/fp/create_vectors64_32.sh b/tests/fp/create_vectors64_32.sh deleted file mode 100755 index db6117c9..00000000 --- a/tests/fp/create_vectors64_32.sh +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh - -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f64_to_f32 > $OUTPUT/f64_f32_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_f32 > $OUTPUT/f64_f32_rz.tv -$BUILD/testfloat_gen -rmax f64_to_f32 > $OUTPUT/f64_f32_ru.tv -$BUILD/testfloat_gen -rmin f64_to_f32 > $OUTPUT/f64_f32_rd.tv - -$BUILD/testfloat_gen -rnear_even f64_to_i32 > $OUTPUT/f64_i32_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_i32 > $OUTPUT/f64_i32_rz.tv -$BUILD/testfloat_gen -rmax f64_to_i32 > $OUTPUT/f64_i32_ru.tv -$BUILD/testfloat_gen -rmin f64_to_i32 > $OUTPUT/f64_i32_rd.tv - -$BUILD/testfloat_gen -rnear_even f64_to_ui32 > $OUTPUT/f64_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_ui32 > $OUTPUT/f64_ui32_rz.tv -$BUILD/testfloat_gen -rmax f64_to_ui32 > $OUTPUT/f64_ui32_ru.tv -$BUILD/testfloat_gen -rmin f64_to_ui32 > $OUTPUT/f64_ui32_rd.tv - - - diff --git a/tests/fp/create_vectors64cmp.sh b/tests/fp/create_vectors64cmp.sh deleted file mode 100755 index 7f5f8c0b..00000000 --- a/tests/fp/create_vectors64cmp.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen f64_eq > $OUTPUT/f64_cmp_eq.tv -$BUILD/testfloat_gen f64_le > $OUTPUT/f64_cmp_le.tv -$BUILD/testfloat_gen f64_lt > $OUTPUT/f64_cmp_lt.tv - -$BUILD/testfloat_gen f64_eq_signaling > $OUTPUT/f64_cmp_eq_signaling.tv -$BUILD/testfloat_gen f64_le_quiet > $OUTPUT/f64_cmp_le_quiet.tv -$BUILD/testfloat_gen f64_lt_quiet > $OUTPUT/f64_cmp_lt_quiet.tv - diff --git a/tests/fp/create_vectors64fma.sh b/tests/fp/create_vectors64fma.sh deleted file mode 100755 index 615245b3..00000000 --- a/tests/fp/create_vectors64fma.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh - -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv -$BUILD/testfloat_gen -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv -$BUILD/testfloat_gen -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv -$BUILD/testfloat_gen -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv - -# format: X_Y_Z_answer_flags_Frm_Fmt -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv -sed -ie 's/$/_0/' $OUTPUT/f64_mulAdd_rne.tv -sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rne.tv - -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv -sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rz.tv -sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rz.tv - -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv -sed -ie 's/$/_3/' $OUTPUT/f64_mulAdd_ru.tv -sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_ru.tv - -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv -sed -ie 's/$/_2/' $OUTPUT/f64_mulAdd_rd.tv -sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rd.tv - -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv -sed -ie 's/$/_4/' $OUTPUT/f64_mulAdd_rnm.tv -sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rnm.tv \ No newline at end of file diff --git a/tests/fp/create_vectorsi.sh b/tests/fp/create_vectorsi.sh deleted file mode 100755 index 5d753e50..00000000 --- a/tests/fp/create_vectorsi.sh +++ /dev/null @@ -1,64 +0,0 @@ -#!/bin/sh - -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" - -$BUILD/testfloat_gen -rnear_even -i32_to_f64 > $OUTPUT/i32_f64_rne.tv -$BUILD/testfloat_gen -rminMag -i32_to_f64 > $OUTPUT/i32_f64_rz.tv -$BUILD/testfloat_gen -rmax -i32_to_f64 > $OUTPUT/i32_f64_ru.tv -$BUILD/testfloat_gen -rmin -i32_to_f64 > $OUTPUT/i32_f64_rd.tv - -$BUILD/testfloat_gen -rnear_even -i64_to_f64 > $OUTPUT/i64_f64_rne.tv -$BUILD/testfloat_gen -rminMag -i64_to_f64 > $OUTPUT/i64_f64_rz.tv -$BUILD/testfloat_gen -rmax -i64_to_f64 > $OUTPUT/i64_f64_ru.tv -$BUILD/testfloat_gen -rmin -i64_to_f64 > $OUTPUT/i64_f64_rd.tv - -$BUILD/testfloat_gen -rnear_even -i32_to_f32 > $OUTPUT/i32_f32_rne.tv -$BUILD/testfloat_gen -rminMag -i32_to_f32 > $OUTPUT/i32_f32_rz.tv -$BUILD/testfloat_gen -rmax -i32_to_f32 > $OUTPUT/i32_f32_ru.tv -$BUILD/testfloat_gen -rmin -i32_to_f32 > $OUTPUT/i32_f32_rd.tv - -$BUILD/testfloat_gen -rnear_even -f32_to_i32 > $OUTPUT/f32_i32_rne.tv -$BUILD/testfloat_gen -rminMag -f32_to_i32 > $OUTPUT/f32_i32_rz.tv -$BUILD/testfloat_gen -rmax -f32_to_i32 > $OUTPUT/f32_i32_ru.tv -$BUILD/testfloat_gen -rmin -f32_to_i32 > $OUTPUT/f32_i32_rd.tv - -$BUILD/testfloat_gen -rnear_even -f32_to_ui32 > $OUTPUT/f32_ui32_rne.tv -$BUILD/testfloat_gen -rminMag -f32_to_ui32 > $OUTPUT/f32_ui32_rz.tv -$BUILD/testfloat_gen -rmax -f32_to_ui32 > $OUTPUT/f32_ui32_ru.tv -$BUILD/testfloat_gen -rmin -f32_to_ui32 > $OUTPUT/f32_ui32_rd.tv - -$BUILD/testfloat_gen -rnear_even -i64_to_f32 > $OUTPUT/i64_f32_rne.tv -$BUILD/testfloat_gen -rminMag -i64_to_f32 > $OUTPUT/i64_f32_rz.tv -$BUILD/testfloat_gen -rmax -i64_to_f32 > $OUTPUT/i64_f32_ru.tv -$BUILD/testfloat_gen -rmin -i64_to_f32 > $OUTPUT/i64_f32_rd.tv - -$BUILD/testfloat_gen -rnear_even -ui32_to_f64 > $OUTPUT/ui32_f64_rne.tv -$BUILD/testfloat_gen -rminMag -ui32_to_f64 > $OUTPUT/ui32_f64_rz.tv -$BUILD/testfloat_gen -rmax -ui32_to_f64 > $OUTPUT/ui32_f64_ru.tv -$BUILD/testfloat_gen -rmin -ui32_to_f64 > $OUTPUT/ui32_f64_rd.tv - -$BUILD/testfloat_gen -rnear_even -ui64_to_f64 > $OUTPUT/ui64_f64_rne.tv -$BUILD/testfloat_gen -rminMag -ui64_to_f64 > $OUTPUT/ui64_f64_rz.tv -$BUILD/testfloat_gen -rmax -ui64_to_f64 > $OUTPUT/ui64_f64_ru.tv -$BUILD/testfloat_gen -rmin -ui64_to_f64 > $OUTPUT/ui64_f64_rd.tv - -$BUILD/testfloat_gen -rnear_even -ui32_to_f32 > $OUTPUT/ui32_f32_rne.tv -$BUILD/testfloat_gen -rminMag -ui32_to_f32 > $OUTPUT/ui32_f32_rz.tv -$BUILD/testfloat_gen -rmax -ui32_to_f32 > $OUTPUT/ui32_f32_ru.tv -$BUILD/testfloat_gen -rmin -ui32_to_f32 > $OUTPUT/ui32_f32_rd.tv - -$BUILD/testfloat_gen -rnear_even -ui64_to_f32 > $OUTPUT/ui64_f32_rne.tv -$BUILD/testfloat_gen -rminMag -ui64_to_f32 > $OUTPUT/ui64_f32_rz.tv -$BUILD/testfloat_gen -rmax -ui64_to_f32 > $OUTPUT/ui64_f32_ru.tv -$BUILD/testfloat_gen -rmin -ui64_to_f32 > $OUTPUT/ui64_f32_rd.tv - -$BUILD/testfloat_gen -rnear_even -f64_to_i64 > $OUTPUT/f64_i64_rne.tv -$BUILD/testfloat_gen -rminMag -f64_to_i64 > $OUTPUT/f64_i64_rz.tv -$BUILD/testfloat_gen -rmax -f64_to_i64 > $OUTPUT/f64_i64_ru.tv -$BUILD/testfloat_gen -rmin -f64_to_i64 > $OUTPUT/f64_i64_rd.tv - -$BUILD/testfloat_gen -rnear_even -f64_to_ui64 > $OUTPUT/f64_ui64_rne.tv -$BUILD/testfloat_gen -rminMag -f64_to_ui64 > $OUTPUT/f64_ui64_rz.tv -$BUILD/testfloat_gen -rmax -f64_to_ui64 > $OUTPUT/f64_ui64_ru.tv -$BUILD/testfloat_gen -rmin -f64_to_ui64 > $OUTPUT/f64_ui64_rd.tv diff --git a/tests/fp/remove_spaces.sh b/tests/fp/remove_spaces.sh new file mode 100755 index 00000000..ed6106fd --- /dev/null +++ b/tests/fp/remove_spaces.sh @@ -0,0 +1,483 @@ +#!/bin/sh +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" +OUTPUT="./vectors" +echo "Editing ui32_to_f16 test vectors" +sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rne.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rz.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_ru.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rd.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rnm.tv +echo "Editing ui32_to_f32 test vectors" +sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rne.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rz.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_ru.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rd.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rnm.tv +echo "Editing ui32_to_f64 test vectors" +sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rne.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rz.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_ru.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rd.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rnm.tv +echo "Editing ui32_to_f128 test vectors" +sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rne.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rz.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_ru.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rd.tv +sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rnm.tv +echo "Editing ui64_to_f16 test vectors" +sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rne.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rz.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_ru.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rd.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rnm.tv +echo "Editing ui64_to_f32 test vectors" +sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rne.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rz.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_ru.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rd.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rnm.tv +echo "Editing ui64_to_f64 test vectors" +sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rne.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rz.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_ru.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rd.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rnm.tv +echo "Editing ui64_to_f128 test vectors" +sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rne.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rz.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_ru.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rd.tv +sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rnm.tv +echo "Editing i32_to_f16 test vectors" +sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rne.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rz.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f16_ru.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rd.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rnm.tv +echo "Editing i32_to_f32 test vectors" +sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rne.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rz.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f32_ru.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rd.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rnm.tv +echo "Editing i32_to_f64 test vectors" +sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rne.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rz.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f64_ru.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rd.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rnm.tv +echo "Editing i32_to_f128 test vectors" +sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rne.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rz.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f128_ru.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rd.tv +sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rnm.tv +echo "Editing i64_to_f16 test vectors" +sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rne.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rz.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f16_ru.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rd.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rnm.tv +echo "Editing i64_to_f32 test vectors" +sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rne.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rz.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f32_ru.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rd.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rnm.tv +echo "Editing i64_to_f64 test vectors" +sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rne.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rz.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f64_ru.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rd.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rnm.tv +echo "Editing i64_to_f128 test vectors" +sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rne.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rz.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f128_ru.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rd.tv +sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rnm.tv +echo "Editing f16_to_ui32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rnm.tv +echo "Editing f32_to_ui32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rnm.tv +echo "Editing f64_to_ui32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rnm.tv +echo "Editing f128_to_ui32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rnm.tv +echo "Editing f16_to_ui64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rnm.tv +echo "Editing f32_to_ui64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rnm.tv +echo "Editing f64_to_ui64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rnm.tv +echo "Editing f128_to_ui64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rnm.tv +echo "Editing f16_to_i32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_i32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rnm.tv +echo "Editing f32_to_i32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_i32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rnm.tv +echo "Editing f64_to_i32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_i32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rnm.tv +echo "Editing f128_to_i32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_i32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rnm.tv +echo "Editing f16_to_i64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_i64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rnm.tv +echo "Editing f32_to_i64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_i64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rnm.tv +echo "Editing f64_to_i64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_i64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rnm.tv +echo "Editing f128_to_i64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_i64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rnm.tv +echo "Editing f16_to_f32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rnm.tv +echo "Editing f16_to_f64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rnm.tv +echo "Editing f16_to_f128 test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f128_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rnm.tv +echo "Editing f32_to_f16 test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f16_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rnm.tv +echo "Editing f32_to_f64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rnm.tv +echo "Editing f32_to_f128 test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f128_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rnm.tv +echo "Editing f64_to_f16 test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f16_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rnm.tv +echo "Editing f64_to_f32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rnm.tv +echo "Editing f64_to_f128 test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f128_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rnm.tv +echo "Editing f128_to_f16 test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f16_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rnm.tv +echo "Editing f128_to_f32 test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f32_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rnm.tv +echo "Editing f128_to_f64 test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f64_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rnm.tv +echo "Editing f16_add test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_add_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_add_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_add_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_add_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_add_rnm.tv +echo "Editing f32_add test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_add_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_add_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_add_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_add_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_add_rnm.tv +echo "Editing f64_add test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_add_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_add_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_add_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_add_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_add_rnm.tv +echo "Editing f128_add test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_add_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_add_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_add_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_add_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_add_rnm.tv +echo "Editing f16_sub test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_sub_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_sub_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_sub_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_sub_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_sub_rnm.tv +echo "Editing f32_sub test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_sub_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_sub_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_sub_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_sub_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_sub_rnm.tv +echo "Editing f64_sub test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_sub_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_sub_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_sub_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_sub_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_sub_rnm.tv +echo "Editing f128_sub test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_sub_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_sub_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_sub_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_sub_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_sub_rnm.tv +echo "Editing f16_mul test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_mul_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_mul_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_mul_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_mul_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_mul_rnm.tv +echo "Editing f32_mul test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_mul_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_mul_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_mul_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_mul_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_mul_rnm.tv +echo "Editing f64_mul test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_mul_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_mul_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_mul_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_mul_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_mul_rnm.tv +echo "Editing f128_mul test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_mul_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_mul_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_mul_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_mul_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_mul_rnm.tv +echo "Editing f16_div test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_div_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_div_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_div_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_div_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_div_rnm.tv +echo "Editing f32_div test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_div_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_div_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_div_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_div_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_div_rnm.tv +echo "Editing f64_div test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_div_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_div_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_div_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_div_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_div_rnm.tv +echo "Editing f128_div test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_div_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_div_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_div_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_div_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_div_rnm.tv +echo "Editing f16_sqrt test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_sqrt_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rnm.tv +echo "Editing f32_sqrt test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_sqrt_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rnm.tv +echo "Editing f64_sqrt test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_sqrt_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rnm.tv +echo "Editing f128_sqrt test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_sqrt_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rnm.tv +echo "Editing f16_eq test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_eq_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_eq_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_eq_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_eq_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_eq_rnm.tv +echo "Editing f32_eq test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_eq_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_eq_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_eq_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_eq_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_eq_rnm.tv +echo "Editing f64_eq test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_eq_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_eq_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_eq_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_eq_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_eq_rnm.tv +echo "Editing f128_eq test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_eq_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_eq_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_eq_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_eq_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_eq_rnm.tv +echo "Editing f16_le test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_le_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_le_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_le_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_le_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_le_rnm.tv +echo "Editing f32_le test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_le_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_le_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_le_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_le_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_le_rnm.tv +echo "Editing f64_le test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_le_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_le_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_le_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_le_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_le_rnm.tv +echo "Editing f128_le test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_le_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_le_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_le_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_le_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_le_rnm.tv +echo "Editing f16_lt test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_lt_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_lt_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_lt_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_lt_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_lt_rnm.tv +echo "Editing f32_lt test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_lt_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_lt_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_lt_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_lt_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_lt_rnm.tv +echo "Editing f64_lt test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_lt_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_lt_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_lt_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_lt_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_lt_rnm.tv +echo "Editing f128_lt test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_lt_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_lt_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_lt_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_lt_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_lt_rnm.tv +echo "Editing f16_mulAdd test vectors" +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv +echo "Editing f32_mulAdd test vectors" +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv +echo "Editing f64_mulAdd test vectors" +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv +echo "Editing f128_mulAdd test vectors" +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv diff --git a/tests/fp/run_all.sh b/tests/fp/run_all.sh index d34366b9..9c45ff2d 100755 --- a/tests/fp/run_all.sh +++ b/tests/fp/run_all.sh @@ -1,14 +1,5 @@ #!/bin/sh -./create_vectors16.sh -./create_vectors32_64.sh -./create_vectors32cmp.sh -./create_vectors32.sh -./create_vectors64_32.sh -./create_vectors64cmp.sh -./create_vectors64.sh -./create_vectorsi.sh -./create_vectors16fma.sh -./create_vectors32fma.sh -./create_vectors64fma.sh -./create_vectors128fma.sh +./create_vectors.sh +./remove_spaces.sh +./append_ctrlSig.sh diff --git a/tests/fp/undy.sh b/tests/fp/undy.sh deleted file mode 100755 index 887dbeaf..00000000 --- a/tests/fp/undy.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -sed -i 's/ /_/g' $1