From c3cc2f98d6f367bc8bd091fca728299d0d4fa8c8 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 16 Feb 2023 18:10:05 -0800
Subject: [PATCH] Reverted lab3 changes in dev branch

---
 src/ieu/alu.sv         | 2 +-
 src/ieu/controller.sv  | 2 +-
 src/ieu/datapath.sv    | 2 +-
 testbench/testbench.sv | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
index 3f25e6de..ccd55779 100644
--- a/src/ieu/alu.sv
+++ b/src/ieu/alu.sv
@@ -68,7 +68,7 @@ module alu #(parameter WIDTH=32) (
  
   // SLT
   assign SLT = {{(WIDTH-1){1'b0}}, LT};
-  assign SLTU = {{(WIDTH-1){1'b0}}, LT};
+  assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
  
   // Select appropriate ALU Result
   always_comb
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index cafe7d3d..d6642534 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -99,7 +99,7 @@ module controller(
   logic        CSRWriteD, CSRWriteE;           // CSR write
   logic        PrivilegedD, PrivilegedE;       // Privileged instruction
   logic        InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
-  logic        ControlsD;                // Main Instruction Decoder control signals
+  logic [`CTRLW-1:0] ControlsD;                // Main Instruction Decoder control signals
   logic        SubArithD;                      // TRUE for R-type subtracts and sra, slt, sltu
   logic        subD, sraD, sltD, sltuD;        // Indicates if is one of these instructions
   logic        BranchTakenE;                   // Branch is taken
diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv
index 07bd4fae..60d43de9 100644
--- a/src/ieu/datapath.sv
+++ b/src/ieu/datapath.sv
@@ -101,7 +101,7 @@ module datapath (
   flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
   flopenrc #(`XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE);
   flopenrc #(5)     Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
-  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs1E);
+  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
   flopenrc #(5)     RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
 	
   mux3  #(`XLEN)  faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index b9046452..61143b12 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -281,7 +281,7 @@ logic [3:0] dummy;
         // once the test inidicates it's done we need to immediately hold reset for a number of cycles.
         if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1;
         else begin // hit reset threshold so we remove reset.
-          //InReset = 0; hmmm-I smell a wumpus
+          InReset = 0; 
           ResetCount = 0;
         end
       end else begin