From c2b9fc0d8e556fb13ff5499c170190ad703e9fc6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 12 May 2022 22:26:21 +0000
Subject: [PATCH] trap/csr cleanup

---
 pipelined/src/privileged/csr.sv  | 3 ++-
 pipelined/src/privileged/trap.sv | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index 18ecd01d..6d71b08d 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -59,7 +59,6 @@ module csr #(parameter
   input  logic             SelHPTW,
   output logic [1:0]       STATUS_MPP,
   output logic             STATUS_SPP, STATUS_TSR, STATUS_TVM,
-  output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, 
   output logic [`XLEN-1:0]      MEDELEG_REGW, 
   output logic [`XLEN-1:0] SATP_REGW,
   output logic [11:0]      MIP_REGW, MIE_REGW, MIDELEG_REGW,
@@ -84,6 +83,8 @@ module csr #(parameter
  
 (* mark_debug = "true" *)  logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
   logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW;
+  logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW;
+
   logic [31:0]     MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
   logic            WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
   logic            CSRMWriteM, CSRSWriteM, CSRUWriteM;
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index f23efeba..fe2c7cf1 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -42,7 +42,7 @@ module trap (
   (* mark_debug = "true" *) input logic [11:0] 	   MIP_REGW, MIE_REGW, MIDELEG_REGW,
   input logic 		   STATUS_MIE, STATUS_SIE,
   input logic 		   InstrValidM, CommittedM, 
-  output logic 		   TrapM, MTrapM, STrapM, RetM,
+  output logic 		   TrapM, RetM,
   output logic 		   InterruptM, IntPendingM,
   output logic [`XLEN-1:0] CauseM 
 );