From c281539f36adbd0fbd281445b7caf9c40a998496 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 4 Jul 2021 14:59:04 -0400 Subject: [PATCH] TLB cleanup --- wally-pipelined/src/mmu/priorityencoder.sv | 2 +- wally-pipelined/src/mmu/tlb.sv | 29 +++++-------------- wally-pipelined/src/mmu/tlbcam.sv | 22 +++----------- .../src/mmu/{camline.sv => tlbcamline.sv} | 8 ++--- .../src/mmu/tlbphysicalpagemask.sv | 2 +- wally-pipelined/src/mmu/tlbram.sv | 11 +------ 6 files changed, 19 insertions(+), 55 deletions(-) rename wally-pipelined/src/mmu/{camline.sv => tlbcamline.sv} (93%) diff --git a/wally-pipelined/src/mmu/priorityencoder.sv b/wally-pipelined/src/mmu/priorityencoder.sv index d56da3d6..44ce88da 100644 --- a/wally-pipelined/src/mmu/priorityencoder.sv +++ b/wally-pipelined/src/mmu/priorityencoder.sv @@ -31,7 +31,7 @@ `include "wally-config.vh" -module priorityencoder #(parameter BINARY_BITS = 3) ( +module tlbpriority #(parameter BINARY_BITS = 3) ( input logic [2**BINARY_BITS - 1:0] onehot, output logic [BINARY_BITS - 1:0] binary ); diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index a4326ce8..8aaf6570 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -148,7 +148,6 @@ module tlb #(parameter ENTRY_BITS = 3, assign WriteAccess = TLBAccessType[0]; assign TLBAccess = ReadAccess || WriteAccess; - assign PageOffset = VirtualAddress[11:0]; // TLB entries are evicted according to the LRU algorithm tlblru #(ENTRY_BITS) lru(.*); @@ -157,11 +156,15 @@ module tlb #(parameter ENTRY_BITS = 3, tlbram #(ENTRY_BITS) tlbram(.*); tlbcam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlbcam(.*); + // Replace segments of the virtual page number with segments of the physical + // page number. For 4 KB pages, the entire virtual page number is replaced. + // For superpages, some segments are considered offsets into a larger page. + tlbphysicalpagemask PageMask(VirtualPageNumber, PhysicalPageNumber, HitPageType, PhysicalPageNumberMixed); + // unswizzle useful PTE bits assign {PTE_U, PTE_X, PTE_W, PTE_R} = PTEAccessBits[4:1]; // Check whether the access is allowed, page faulting if not. - // *** We might not have S mode. generate if (ITLB == 1) begin logic ImproperPrivilege; @@ -189,28 +192,12 @@ module tlb #(parameter ENTRY_BITS = 3, end endgenerate - // Replace segments of the virtual page number with segments of the physical - // page number. For 4 KB pages, the entire virtual page number is replaced. - // For superpages, some segments are considered offsets into a larger page. - tlbphysicalpagemask PageMask(VirtualPageNumber, PhysicalPageNumber, HitPageType, PhysicalPageNumberMixed); - - // Provide physical address only on TLBHits to cause catastrophic errors if - // garbage address is used. - assign PhysicalAddressFull = TLBHit ? {PhysicalPageNumberMixed, PageOffset} : '0; // Output the hit physical address if translation is currently on. -/* generate - if (`XLEN == 32) begin - VirtualAddressPALen = {2'b0, VirtualAddress}; - - mux2 #(`PA_BITS) addressmux({2'b0, VirtualAddress}, PhysicalAddressFull, Translate, PhysicalAddress); - end else begin - VirtualAddressPALen = VirtualAddress[`PA_BITS-1:0]; - mux2 #(`PA_BITS) addressmux(VirtualAddress[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress); - end - endgenerate*/ - + // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal assign VAExt = {2'b00, VirtualAddress}; // extend length of virtual address if necessary for RV32 + assign PageOffset = VirtualAddress[11:0]; + assign PhysicalAddressFull = TLBHit ? {PhysicalPageNumberMixed, PageOffset} : '0; mux2 #(`PA_BITS) addressmux(VAExt[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress); assign TLBHit = CAMHit & TLBAccess; diff --git a/wally-pipelined/src/mmu/tlbcam.sv b/wally-pipelined/src/mmu/tlbcam.sv index e45b124a..07ec38ff 100644 --- a/wally-pipelined/src/mmu/tlbcam.sv +++ b/wally-pipelined/src/mmu/tlbcam.sv @@ -34,8 +34,6 @@ module tlbcam #(parameter ENTRY_BITS = 3, input logic clk, reset, input logic [KEY_BITS-1:0] VirtualPageNumber, input logic [1:0] PageTypeWriteVal, -// input logic [`SVMODE_BITS-1:0] SvMode, // *** may not need to be used. -// input logic TLBWrite, input logic TLBFlush, input logic [2**ENTRY_BITS-1:0] WriteEnables, @@ -56,23 +54,11 @@ module tlbcam #(parameter ENTRY_BITS = 3, // of page type. However, matches are determined based on a subset of the // page number segments. - camline #(KEY_BITS, SEGMENT_BITS) camlines[NENTRIES-1:0]( + tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[NENTRIES-1:0]( .CAMLineWrite(WriteEnables), - .PageType(PageTypeList), - .Match(Matches), - .*); -/* - generate - genvar i; - for (i = 0; i < NENTRIES; i++) begin - camline #(KEY_BITS, SEGMENT_BITS) camline( - .CAMLineWrite(WriteEnables[i]), - .PageType(PageTypeList[i]), - .Match(Matches[i]), - .*); - end - endgenerate - */ + .PageType(PageTypeList), + .Match(Matches), + .*); // In case there are multiple matches in the CAM, select only one // *** it might be guaranteed that the CAM will never have multiple matches. diff --git a/wally-pipelined/src/mmu/camline.sv b/wally-pipelined/src/mmu/tlbcamline.sv similarity index 93% rename from wally-pipelined/src/mmu/camline.sv rename to wally-pipelined/src/mmu/tlbcamline.sv index 6e3f705c..3e882cf1 100644 --- a/wally-pipelined/src/mmu/camline.sv +++ b/wally-pipelined/src/mmu/tlbcamline.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// camline.sv +// tlbcamline.sv // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 6 April 2021 // Modified: kmacsaigoren@hmc.edu 1 June 2021 @@ -28,7 +28,7 @@ `include "wally-config.vh" -module camline #(parameter KEY_BITS = 20, +module tlbcamline #(parameter KEY_BITS = 20, parameter SEGMENT_BITS = 10) ( input logic clk, reset, @@ -85,12 +85,12 @@ module camline #(parameter KEY_BITS = 20, assign {Key3, Key2, Key1, Key0} = Key; // Calculate the actual match value based on the input vpn and the page type. - // For example, a gigapage in SV only cares about VPN[2], so VPN[0] and VPN[1] + // For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1] // should automatically match. assign Match0 = (Query0 == Key0) || (PageType > 2'd0); // least signifcant section assign Match1 = (Query1 == Key1) || (PageType > 2'd1); assign Match2 = (Query2 == Key2) || (PageType > 2'd2); - assign Match3 = (Query3 == Key3); // *** this should always match in sv39 since both vPN3 and key3 are zeroed by the pagetable walker before getting to the cam + assign Match3 = (Query3 == Key3); // this should always match in sv39 since both vPN3 and key3 are zeroed by the pagetable walker before getting to the cam assign Match = Match0 & Match1 & Match2 & Match3 & Valid; end diff --git a/wally-pipelined/src/mmu/tlbphysicalpagemask.sv b/wally-pipelined/src/mmu/tlbphysicalpagemask.sv index 858c3939..dd791e48 100644 --- a/wally-pipelined/src/mmu/tlbphysicalpagemask.sv +++ b/wally-pipelined/src/mmu/tlbphysicalpagemask.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -module physicalpagemask ( +module tlbphysicalpagemask ( input logic [`VPN_BITS-1:0] VPN, input logic [`PPN_BITS-1:0] PPN, input logic [1:0] PageType, diff --git a/wally-pipelined/src/mmu/tlbram.sv b/wally-pipelined/src/mmu/tlbram.sv index f13666bc..9482cd6f 100644 --- a/wally-pipelined/src/mmu/tlbram.sv +++ b/wally-pipelined/src/mmu/tlbram.sv @@ -46,16 +46,7 @@ module tlbram #(parameter ENTRY_BITS = 3) ( // Generate a flop for every entry in the RAM flopenr #(`XLEN) pteflops[NENTRIES-1:0](clk, reset, WriteEnables, PTEWriteVal, ram); -/* - generate - genvar i; - for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops - flopenr #(`XLEN) pteflop(clk, reset, WriteEnables[i], - PTEWriteVal, ram[i]); - end - endgenerate -*/ - + assign PageTableEntry = ram[VPNIndex]; assign PTEAccessBits = PageTableEntry[7:0]; assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];