From c260354817e0a64522aff43e5c7d3a27ac848699 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 6 Jan 2023 05:11:14 -0800
Subject: [PATCH] Removed unused UARCH configuration entries

---
 pipelined/config/buildroot/wally-config.vh  | 5 -----
 pipelined/config/fpga/wally-config.vh       | 5 -----
 pipelined/config/rv32e/wally-config.vh      | 4 ----
 pipelined/config/rv32gc/wally-config.vh     | 6 +-----
 pipelined/config/rv32i/wally-config.vh      | 4 ----
 pipelined/config/rv32ic/wally-config.vh     | 4 ----
 pipelined/config/rv64BP/wally-config.vh     | 5 -----
 pipelined/config/rv64fpquad/wally-config.vh | 5 -----
 pipelined/config/rv64gc/wally-config.vh     | 7 +------
 pipelined/config/rv64i/wally-config.vh      | 5 -----
 pipelined/config/shared/wally-shared.vh     | 4 ++--
 11 files changed, 4 insertions(+), 50 deletions(-)

diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index 0edf6720..56292c84 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -43,11 +43,6 @@
 `define COUNTERS 32
 `define DESIGN_COMPILER 0
 
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-
 // LSU microarchitectural Features
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index a01209c2..c786950d 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -45,11 +45,6 @@
 `define COUNTERS 32
 `define DESIGN_COMPILER 0
 
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-
 // LSU microarchitectural Features
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index 0e222ea4..f029e0e6 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -45,10 +45,6 @@
 `define ZICOUNTERS_SUPPORTED 0
 `define ZFH_SUPPORTED 0
 
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
 `define BUS 1
 `define DCACHE 0
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index fcb0adec..4d346e5a 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -44,10 +44,6 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define ZFH_SUPPORTED 0
 
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
 `define BUS 1
 `define DCACHE 1
@@ -75,7 +71,7 @@
 `define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 64
+`define PMP_ENTRIES 16
 
 // Address space
 `define RESET_VECTOR 32'h80000000
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
index 427e4e5b..7fb355c5 100644
--- a/pipelined/config/rv32i/wally-config.vh
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -45,10 +45,6 @@
 `define ZICOUNTERS_SUPPORTED 0
 `define ZFH_SUPPORTED 0
 
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
 `define BUS 0
 `define DCACHE 0
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index f1f65740..311ce8ab 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -44,10 +44,6 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define ZFH_SUPPORTED 0
 
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
 `define BUS 1
 `define DCACHE 0
diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh
index c03b5042..7b8d4942 100644
--- a/pipelined/config/rv64BP/wally-config.vh
+++ b/pipelined/config/rv64BP/wally-config.vh
@@ -38,7 +38,6 @@
 // IEEE 754 compliance
 `define IEEE754 0
 
-//`define MISA (32'h00000105)
 `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 1
@@ -46,10 +45,6 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define ZFH_SUPPORTED 0
 
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
index 882117e7..2df9867f 100644
--- a/pipelined/config/rv64fpquad/wally-config.vh
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -45,11 +45,6 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define ZFH_SUPPORTED 1
 
-/// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-
 // LSU microarchitectural Features
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index f1f45010..a7d0f34d 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -45,11 +45,6 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define ZFH_SUPPORTED 0
 
-/// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-
 // LSU microarchitectural Features
 `define BUS 1
 `define DCACHE 1
@@ -77,7 +72,7 @@
 `define IDIV_ON_FPU 1
 
 // Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 64
+`define PMP_ENTRIES 16
 
 // Address space
 `define RESET_VECTOR 64'h0000000080000000
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
index a5ccec47..c7304c72 100644
--- a/pipelined/config/rv64i/wally-config.vh
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -45,11 +45,6 @@
 `define ZICOUNTERS_SUPPORTED 0
 `define ZFH_SUPPORTED 0
 
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-
 // LSU microarchitectural Features
 `define BUS 0
 `define DCACHE 0
diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh
index 7d54f50b..f9c46b69 100644
--- a/pipelined/config/shared/wally-shared.vh
+++ b/pipelined/config/shared/wally-shared.vh
@@ -23,8 +23,8 @@
 ///////////////////////////////////////////
 
 // division constants
-`define RADIX       32'h2
-`define DIVCOPIES   32'h1
+`define RADIX       32'h4
+`define DIVCOPIES   32'h2
 
 // Memory synthesis configuration
 `define USE_SRAM 0