diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index a7289d6e..e753549b 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1475,8 +1475,8 @@ string imperas32f[] = '{ `WALLYTEST, "rv64i_m/privilege/WALLY-MMU-SV39", "30A0", "rv64i_m/privilege/WALLY-MMU-SV48", "30A0", - "rv64i_m/privilege/WALLY-PMP", "30A0" -// "rv64i_m/privilege/WALLY-PMA", "30A0", + "rv64i_m/privilege/WALLY-PMP", "30A0", + "rv64i_m/privilege/WALLY-PMA", "30A0" }; string wally64periph[] = '{ @@ -1491,8 +1491,8 @@ string wally32i[] = '{ string wally32priv[] = '{ `WALLYTEST, "rv32i_m/privilege/WALLY-MMU-SV32", "3080", - "rv32i_m/privilege/WALLY-PMP", "3080" -// "rv32i_m/privilege/WALLY-PMA", "3080" + "rv32i_m/privilege/WALLY-PMP", "3080", + "rv32i_m/privilege/WALLY-PMA", "3080" }; string wally32periph[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output index af9973b4..f6266313 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output @@ -1,13 +1,9 @@ -beef00b4 beef00b5 000000b6 -000000b7 +ffffffb7 00000001 00000bad -00000007 -00000005 -00000bad -beef00b9 +00000002 00000007 00000005 00000bad @@ -22,15 +18,9 @@ beef00b9 00000007 00000005 00000bad -00000007 -00000005 -00000bad -000000bf +ffffffbf 00000001 00000bad -00000007 -00000005 -00000bad beef00c1 00000007 00000005 @@ -40,27 +30,37 @@ beef00c1 00000bad 00000001 00000bad -beef00c4 -000000c5 -000000c6 00000007 00000005 00000bad 00000001 00000bad -00000009 -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000007 +00000005 +00000bad +00000001 +00000bad +00000007 +00000005 +00000bad +00000001 +00000bad +00000007 +00000005 +00000bad +00000001 +00000bad +00000007 +00000005 +00000bad +00000001 +00000bad +00000007 +00000005 +00000bad +00000001 +00000bad +0000000b deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S index 0a3ee5fa..778014fe 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S @@ -21,6 +21,19 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// +#define BOOTROM_BASE 0x00001000 +#define BOOTROM_RANGE 0x00000FFF +#define RAM_BASE 0x80000000 +#define RAM_RANGE 0x7FFFFFFF +#define CLINT_BASE 0x02000000 +#define CLINT_RANGE 0x0000FFFF +#define GPIO_BASE 0x10012000 +#define GPIO_RANGE 0x000000FF +#define UART_BASE 0x10000000 +#define UART_RANGE 0x00000007 +#define PLIC_BASE 0x0C000000 +#define PLIC_RANGE 0x03FFFFFF + #include "WALLY-TEST-LIB-32.S" // Test library includes and handler for each type of test, a trap handler, imperas compliance instructions // Ideally this should mean that a test can be written by simply adding .4byte statements as below. @@ -48,92 +61,92 @@ # | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO | # | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO | # | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO | -# | DRAM | 0x80000000 | Any | YES | YES | YES | YES | YES | YES | # ************** Cacheable, Idempotent, Atomic tests are not implemented yet. # ----------------- ROM --------------------- -# *** the rom is read only and these read tests depend on reading a known value out of memory. -# Is there some guaranteed value that I can read out of the ROM -# otherwise the read test can be modified to just check that the read happened, -# not necessarily that it got a known value out of memory. This feels hacky and Id be interested in other options. +# ROM goes untested because it isn't writeable and these tests rely on writing a known value to memory. -# .4byte 0x1000, 0xBEEF0001, 0x0 # 32-bit write: store access fault -# .4byte 0x1000, 0xBEEF0001, 0x1 # 32-bit read: success -# .4byte 0x1000, 0xBEEF0002, 0x12 # 16-bit write: store access fault -# .4byte 0x1000, 0xBEEF0002, 0x15 # 16-bit read: success -# .4byte 0x1000, 0xBEEF0003, 0x13 # 08-bit write: store access fault -# .4byte 0x1000, 0xBEEF0003, 0x16 # 08-bit read: success - -# # *** similar problem with the execute tests. Impossible to write the needed executable code into rom once the program's running -# .4byte 0x1000, 0x111, 0x2 # execute: success # ----------------- CLINT --------------------- -.4byte 0x2000000, 0xBEEF00B5, 0x0 # 32-bit write: success -.4byte 0x2000000, 0xBEEF00B5, 0x1 # 32-bit read: success -.4byte 0x2000000, 0xBEEF00B6, 0x12 # 16-bit write: success -.4byte 0x2000000, 0xBEEF00B6, 0x15 # 16-bit read: success -.4byte 0x2000000, 0xBEEF00B7, 0x13 # 08-bit write: success -.4byte 0x2000000, 0xBEEF00B7, 0x16 # 08-bit read: success +# Use timecmp register as readable and writable section of the CLINT +.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, 0x0 # 32-bit write: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, 0x1 # 32-bit read: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, 0x12 # 16-bit write: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, 0x15 # 16-bit read: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, 0x13 # 08-bit write: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, 0x16 # 08-bit read: success -.4byte 0x2000000, 0xbad, 0x2 # execute: instruction access fault +.4byte CLINT_BASE, 0xbad, 0x2 # execute: instruction access fault # ----------------- PLIC --------------------- -.4byte 0xC000000, 0xBEEF00B9, 0x0 # 32-bit write: success -.4byte 0xC000000, 0xBEEF00B9, 0x1 # 32-bit read: success -.4byte 0xC000000, 0xBEEF00BA, 0x12 # 16-bit write: store access fault -.4byte 0xC000000, 0xBEEF00BA, 0x15 # 16-bit read: load access fault -.4byte 0xC000000, 0xBEEF00BB, 0x13 # 08-bit write: store access fault -.4byte 0xC000000, 0xBEEF00BB, 0x16 # 08-bit read: load access fault +# Write 0x2 instead of wider value to plic address because the register width might change. +.4byte PLIC_BASE + 0x2000, 0x2, 0x0 # 32-bit write: success +.4byte PLIC_BASE + 0x2000, 0x2, 0x1 # 32-bit read: success +.4byte PLIC_BASE, 0xBEEF00BA, 0x12 # 16-bit write: store access fault +.4byte PLIC_BASE, 0xBEEF00BA, 0x15 # 16-bit read: load access fault +.4byte PLIC_BASE, 0xBEEF00BB, 0x13 # 08-bit write: store access fault +.4byte PLIC_BASE, 0xBEEF00BB, 0x16 # 08-bit read: load access fault -.4byte 0xC000000, 0xbad, 0x2 # execute: instruction access fault +.4byte PLIC_BASE, 0xbad, 0x2 # execute: instruction access fault # ----------------- UART0 --------------------- -.4byte 0x10000000, 0xBEEF00BD, 0x0 # 32-bit write: store access fault -.4byte 0x10000000, 0xBEEF00BD, 0x1 # 32-bit read: load access fault -.4byte 0x10000000, 0xBEEF00BE, 0x12 # 16-bit write: store access fault -.4byte 0x10000000, 0xBEEF00BE, 0x15 # 16-bit read: load access fault -.4byte 0x10000000, 0xBEEF00BF, 0x13 # 08-bit write: success -.4byte 0x10000000, 0xBEEF00BF, 0x16 # 08-bit read: success +.4byte UART_BASE, 0xBEEF00BD, 0x0 # 32-bit write: store access fault +.4byte UART_BASE, 0xBEEF00BD, 0x1 # 32-bit read: load access fault +.4byte UART_BASE, 0xBEEF00BE, 0x12 # 16-bit write: store access fault +.4byte UART_BASE, 0xBEEF00BE, 0x15 # 16-bit read: load access fault +# Different address for this test so that we write into a writable register in the uart. +.4byte UART_BASE + 0x3, 0xBEEF00BF, 0x13 # 08-bit write: success +.4byte UART_BASE + 0x3, 0xBEEF00BF, 0x16 # 08-bit read: success -.4byte 0x10000000, 0xbad, 0x2 # execute: instruction access fault +.4byte UART_BASE, 0xbad, 0x2 # execute: instruction access fault # ----------------- GPIO --------------------- -.4byte 0x1012000, 0xBEEF00C1, 0x0 # 32-bit write: success -.4byte 0x1012000, 0xBEEF00C1, 0x1 # 32-bit read: success -.4byte 0x1012000, 0xBEEF00C2, 0x12 # 16-bit write: store access fault -.4byte 0x1012000, 0xBEEF00C2, 0x15 # 16-bit read: load access fault -.4byte 0x1012000, 0xBEEF00C3, 0x13 # 08-bit write: store access fault -.4byte 0x1012000, 0xBEEF00C3, 0x16 # 08-bit read: load access fault +.4byte GPIO_BASE + 0x8, 0xBEEF00C1, 0x0 # 32-bit write: success +.4byte GPIO_BASE + 0x8, 0xBEEF00C1, 0x1 # 32-bit read: success +.4byte GPIO_BASE, 0xBEEF00C2, 0x12 # 16-bit write: store access fault +.4byte GPIO_BASE, 0xBEEF00C2, 0x15 # 16-bit read: load access fault +.4byte GPIO_BASE, 0xBEEF00C3, 0x13 # 08-bit write: store access fault +.4byte GPIO_BASE, 0xBEEF00C3, 0x16 # 08-bit read: load access fault -.4byte 0x1012000, 0xbad, 0x2 # execute: instruction access fault +.4byte GPIO_BASE, 0xbad, 0x2 # execute: instruction access fault -# ----------------- DRAM --------------------- - -# the following is already tested by the fact that this test runs without error: -# 32 bit reads and writes into DRAM, -# Execution in DRAM -# offset by 0xf000 to avoid overwriting the program -.4byte 0x8000F000, 0xBEEF00C5, 0x12 # 16-bit write: success -.4byte 0x8000F000, 0xBEEF00C5, 0x15 # 16-bit read: success -.4byte 0x8000F000, 0xBEEF00C6, 0x13 # 08-bit write: success -.4byte 0x8000F000, 0xBEEF00C6, 0x16 # 08-bit read: success # ----------------- Inaccessible --------------------- # show that load, store, and jalr cause faults in a region not defined by PMAs. -# *** should I go through every possible inaccessible region of memory or is one just fine? -.4byte 0xD000000, 0xBEEF00C7, 0x0 # 32-bit write: store access fault -.4byte 0xD000000, 0xBEEF00C7, 0x1 # 32-bit read: load access fault -.4byte 0x1000, 0x111, 0x2 # execute: instruction access fault +# Tests 'random' place in unimplemented memory +.4byte 0x40000000, 0xBEEF00C7, 0x0 # 32-bit write: store access fault +.4byte 0x40000000, 0xBEEF00C7, 0x1 # 32-bit read: load access fault +.4byte 0x40000000, 0x111, 0x2 # execute: instruction access fault -.4byte 0x0, 0x0, 0x3 // terminate tests +# Tests just past the end of each peripheral +.4byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0xBEEF00C8, 0x0 # 32-bit write: store access fault +.4byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0xBEEF00C8, 0x1 # 32-bit read: load access fault +.4byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x111, 0x2 # execute: instruction access fault +.4byte (CLINT_BASE+CLINT_RANGE+1), 0xBEEF00C9, 0x0 # 32-bit write: store access fault +.4byte (CLINT_BASE+CLINT_RANGE+1), 0xBEEF00C9, 0x1 # 32-bit read: load access fault +.4byte (CLINT_BASE+CLINT_RANGE+1), 0x111, 0x2 # execute: instruction access fault + +.4byte (PLIC_BASE+PLIC_RANGE+1), 0xBEEF00CA, 0x0 # 32-bit write: store access fault +.4byte (PLIC_BASE+PLIC_RANGE+1), 0xBEEF00CA, 0x1 # 32-bit read: load access fault +.4byte (PLIC_BASE+PLIC_RANGE+1), 0x111, 0x2 # execute: instruction access fault + +.4byte (UART_BASE+UART_RANGE+1), 0xBEEF00CB, 0x13 # 08-bit write: store access fault +.4byte (UART_BASE+UART_RANGE+1), 0xBEEF00CB, 0x16 # 08-bit read: load access fault +.4byte (UART_BASE+UART_RANGE+1), 0x111, 0x2 # execute: instruction access fault + +.4byte (GPIO_BASE+GPIO_RANGE+1), 0xBEEF00CC, 0x0 # 32-bit write: store access fault +.4byte (GPIO_BASE+GPIO_RANGE+1), 0xBEEF00CC, 0x1 # 32-bit read: load access fault +.4byte (GPIO_BASE+GPIO_RANGE+1), 0x111, 0x2 # execute: instruction access fault + +.4byte 0x0, 0x0, 0x3 # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output index 3999d10e..7ba4cff9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output @@ -1,11 +1,11 @@ beef00b4 0000dead beef00b5 -00000000 +ffffffff 000000b6 00000000 -000000b7 -00000000 +ffffffb7 +ffffffff 00000001 00000000 00000bad @@ -16,7 +16,7 @@ beef00b5 00000000 00000bad 00000000 -beef00b9 +00000002 00000000 00000007 00000000 @@ -52,8 +52,8 @@ beef00b9 00000000 00000bad 00000000 -000000bf -00000000 +ffffffbf +ffffffff 00000001 00000000 00000bad @@ -65,7 +65,7 @@ beef00b9 00000bad 00000000 beef00c1 -00000000 +ffffffff 00000007 00000000 00000005 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S index f1669d72..7a6a7075 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S @@ -21,7 +21,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#define BOOTROM_BASE 0x00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +#define BOOTROM_BASE 0x00001000 #define BOOTROM_RANGE 0x00000FFF #define RAM_BASE 0x80000000 #define RAM_RANGE 0x7FFFFFFF @@ -70,88 +70,90 @@ # ----------------- CLINT --------------------- -.8byte CLINT_BASE, 0xEEEEEEEEEEEEEEEE, 0x0 # 64-bit write: success -.8byte CLINT_BASE, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success -.8byte CLINT_BASE, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success -.8byte CLINT_BASE, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success -.8byte CLINT_BASE, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success -.8byte CLINT_BASE, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success -.8byte CLINT_BASE, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success -.8byte CLINT_BASE, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success +# Use timecmp register as readable and writable section of the CLINT +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, 0x0 # 64-bit write: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success -.8byte CLINT_BASE, 0xbad, 0x2 # execute: instruction access fault +.8byte CLINT_BASE, 0xbad, 0x2 # execute: instruction access fault # ----------------- PLIC --------------------- -.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault -.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault -.8byte PLIC_BASE, 0x0000DEADBEEF00B9, 0x11 # 32-bit write: success -.8byte PLIC_BASE, 0x0000DEADBEEF00B9, 0x14 # 32-bit read: success -.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault -.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault -.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault -.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault +.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault +.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault +# Write 0x2 instead of wider value to plic address because the register width might change. +.8byte PLIC_BASE + 0x2000, 0x2, 0x11 # 32-bit write: success +.8byte PLIC_BASE + 0x2000, 0x2, 0x14 # 32-bit read: success +.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault +.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault +.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault +.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault -.8byte PLIC_BASE, 0xbad, 0x2 # execute: instruction access fault +.8byte PLIC_BASE, 0xbad, 0x2 # execute: instruction access fault # ----------------- UART0 --------------------- -.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault -.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault -.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault -.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault -.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault -.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault -.8byte UART_BASE, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success -.8byte UART_BASE, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success +.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault +.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault +.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault +.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault +.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault +.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault +# Different address for this test so that we write into a writable register in the uart. +.8byte UART_BASE + 0x3, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success +.8byte UART_BASE + 0x3, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success -.8byte UART_BASE, 0xbad, 0x2 # execute: instruction access fault +.8byte UART_BASE, 0xbad, 0x2 # execute: instruction access fault # ----------------- GPIO --------------------- -.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault -.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault -.8byte GPIO_BASE, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success -.8byte GPIO_BASE, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success -.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault -.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault -.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault -.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault +.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault +.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault +.8byte GPIO_BASE + 0x8, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success +.8byte GPIO_BASE + 0x8, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success +.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault +.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault +.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault +.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault -.8byte GPIO_BASE, 0xbad, 0x2 # execute: instruction access fault +.8byte GPIO_BASE, 0xbad, 0x2 # execute: instruction access fault # ----------------- Inaccessible --------------------- -# show that load, store, and jalr cause faults in a region not defined by PMAs. -# *** should I go through every possible inaccessible region of memory or is one just fine? +# show that load, store, and jalr cause faults in regions not defined by PMAs. # Tests 'random' place in unimplemented memory -.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault -.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault -.8byte 0xD000000, 0x111, 0x2 # execute: instruction access fault +.8byte 0x40000000, 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault +.8byte 0x40000000, 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault +.8byte 0x40000000, 0x111, 0x2 # execute: instruction access fault # Tests just past the end of each peripheral -.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault -.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault +.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C8, 0x0 # 64-bit write: store access fault +.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C8, 0x1 # 64-bit read: load access fault .8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x111, 0x2 # execute: instruction access fault -.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault -.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault +.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C9, 0x0 # 64-bit write: store access fault +.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C9, 0x1 # 64-bit read: load access fault .8byte (CLINT_BASE+CLINT_RANGE+1), 0x111, 0x2 # execute: instruction access fault -.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00C7, 0x11 # 32-bit write: store access fault -.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00C7, 0x14 # 32-bit read: load access fault +.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00CA, 0x11 # 32-bit write: store access fault +.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00CA, 0x14 # 32-bit read: load access fault .8byte (PLIC_BASE+PLIC_RANGE+1), 0x111, 0x2 # execute: instruction access fault -.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00C7, 0x13 # 08-bit write: store access fault -.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00C7, 0x16 # 08-bit read: load access fault +.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00CB, 0x13 # 08-bit write: store access fault +.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00CB, 0x16 # 08-bit read: load access fault .8byte (UART_BASE+UART_RANGE+1), 0x111, 0x2 # execute: instruction access fault -.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00C7, 0x11 # 32-bit write: store access fault -.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00C7, 0x14 # 32-bit read: load access fault +.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00CC, 0x11 # 32-bit write: store access fault +.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00CC, 0x14 # 32-bit read: load access fault .8byte (GPIO_BASE+GPIO_RANGE+1), 0x111, 0x2 # execute: instruction access fault -.8byte 0x0, 0x0, 0x3 // terminate tests +.8byte 0x0, 0x0, 0x3 # terminate tests