From 175e824a618206ee348df407ea84c97712613ba9 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 4 Oct 2022 17:33:49 +0000 Subject: [PATCH 1/3] Renamed endianswap to match module name --- pipelined/regression/sim-wally-batch | 2 +- pipelined/src/lsu/bigendianswap.sv | 79 ---------------------------- 2 files changed, 1 insertion(+), 80 deletions(-) delete mode 100644 pipelined/src/lsu/bigendianswap.sv diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch index afaf935c..e9a387d0 100755 --- a/pipelined/regression/sim-wally-batch +++ b/pipelined/regression/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-pipelined-batch.do rv32ic arch32i" +vsim -c -do "do wally-pipelined-batch.do rv32gc wally32priv" diff --git a/pipelined/src/lsu/bigendianswap.sv b/pipelined/src/lsu/bigendianswap.sv deleted file mode 100644 index e621afcf..00000000 --- a/pipelined/src/lsu/bigendianswap.sv +++ /dev/null @@ -1,79 +0,0 @@ -/////////////////////////////////////////// -// endianswap.sv -// -// Written: David_Harris@hmc.edu 7 May 2022 -// Modified: -// -// Purpose: Swap byte order for Big-Endian accesses -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module endianswap #(parameter LEN=`XLEN) ( - input logic BigEndianM, - input logic [LEN-1:0] a, - output logic [LEN-1:0] y); - - if(LEN == 128) begin - always_comb - if (BigEndianM) begin // swap endianness - y[127:120] = a[7:0]; - y[119:112] = a[15:8]; - y[111:104] = a[23:16]; - y[103:96] = a[31:24]; - y[95:88] = a[39:32]; - y[87:80] = a[47:40]; - y[79:72] = a[55:48]; - y[71:64] = a[63:56]; - y[63:56] = a[71:64]; - y[55:48] = a[79:72]; - y[47:40] = a[87:80]; - y[39:32] = a[95:88]; - y[31:24] = a[103:96]; - y[23:16] = a[111:104]; - y[15:8] = a[119:112]; - y[7:0] = a[127:120]; - end else y = a; - end else if(LEN == 64) begin - always_comb - if (BigEndianM) begin // swap endianness - y[63:56] = a[7:0]; - y[55:48] = a[15:8]; - y[47:40] = a[23:16]; - y[39:32] = a[31:24]; - y[31:24] = a[39:32]; - y[23:16] = a[47:40]; - y[15:8] = a[55:48]; - y[7:0] = a[63:56]; - end else y = a; - end else begin - always_comb - if (BigEndianM) begin - y[31:24] = a[7:0]; - y[23:16] = a[15:8]; - y[15:8] = a[23:16]; - y[7:0] = a[31:24]; - end else y = a; - end -endmodule From 2bbcec680fb7862722c2204b944f589a080daef6 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 4 Oct 2022 17:37:05 +0000 Subject: [PATCH 2/3] addded renamed file --- pipelined/src/lsu/endianswap.sv | 79 +++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 pipelined/src/lsu/endianswap.sv diff --git a/pipelined/src/lsu/endianswap.sv b/pipelined/src/lsu/endianswap.sv new file mode 100644 index 00000000..e621afcf --- /dev/null +++ b/pipelined/src/lsu/endianswap.sv @@ -0,0 +1,79 @@ +/////////////////////////////////////////// +// endianswap.sv +// +// Written: David_Harris@hmc.edu 7 May 2022 +// Modified: +// +// Purpose: Swap byte order for Big-Endian accesses +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module endianswap #(parameter LEN=`XLEN) ( + input logic BigEndianM, + input logic [LEN-1:0] a, + output logic [LEN-1:0] y); + + if(LEN == 128) begin + always_comb + if (BigEndianM) begin // swap endianness + y[127:120] = a[7:0]; + y[119:112] = a[15:8]; + y[111:104] = a[23:16]; + y[103:96] = a[31:24]; + y[95:88] = a[39:32]; + y[87:80] = a[47:40]; + y[79:72] = a[55:48]; + y[71:64] = a[63:56]; + y[63:56] = a[71:64]; + y[55:48] = a[79:72]; + y[47:40] = a[87:80]; + y[39:32] = a[95:88]; + y[31:24] = a[103:96]; + y[23:16] = a[111:104]; + y[15:8] = a[119:112]; + y[7:0] = a[127:120]; + end else y = a; + end else if(LEN == 64) begin + always_comb + if (BigEndianM) begin // swap endianness + y[63:56] = a[7:0]; + y[55:48] = a[15:8]; + y[47:40] = a[23:16]; + y[39:32] = a[31:24]; + y[31:24] = a[39:32]; + y[23:16] = a[47:40]; + y[15:8] = a[55:48]; + y[7:0] = a[63:56]; + end else y = a; + end else begin + always_comb + if (BigEndianM) begin + y[31:24] = a[7:0]; + y[23:16] = a[15:8]; + y[15:8] = a[23:16]; + y[7:0] = a[31:24]; + end else y = a; + end +endmodule From d5cd67cf09c5d0f877796222a21e40188195e517 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 4 Oct 2022 17:37:39 +0000 Subject: [PATCH 3/3] fixed endianness mstatush problem, passes make, not regression --- pipelined/testbench/tests.vh | 6 ++++-- .../rv32i_m/privilege/src/WALLY-endianness-01.S | 17 ++++++++++------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 61e76ff1..b6c7c790 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1818,7 +1818,8 @@ string imperas32f[] = '{ "rv64i_m/privilege/src/WALLY-trap-sret-01.S", "rv64i_m/privilege/src/WALLY-trap-u-01.S", "rv64i_m/privilege/src/WALLY-wfi-01.S", - "rv64i_m/privilege/src/WALLY-endianness-01.S" + "rv64i_m/privilege/src/WALLY-endianness-01.S", + "rv64i_m/privilege/src/WALLY-status-xlen-01.S" }; string wally64periph[] = '{ @@ -1896,7 +1897,8 @@ string imperas32f[] = '{ "rv32i_m/privilege/src/WALLY-trap-s-01.S", "rv32i_m/privilege/src/WALLY-trap-sret-01.S", "rv32i_m/privilege/src/WALLY-trap-u-01.S", - "rv32i_m/privilege/src/WALLY-wfi-01.S" + "rv32i_m/privilege/src/WALLY-wfi-01.S", + "rv32i_m/privilege/src/WALLY-endianness-01.S" }; string wally32periph[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S index e51a6b65..c13dde25 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S @@ -58,7 +58,7 @@ addi t1, t1, 4 addi a6, a6, 4 li x28, 0x20 -csrs mstatush, x28 // turn on big endianness for M mode +csrs 0x310, x28 // turn on big endianness for M mode // using '0x310' instead of mstatush because GCC doesn't recognize just mstatush // M mode Big endianness tests // In big endian modes, all values are sign extended to the right, rather than left @@ -83,7 +83,7 @@ addi t1, t1, 4 addi a6, a6, 4 li x28, 0x20 -csrc mstatush, x28 // Turn off big endianness for M mode before going into the trap handler +csrc 0x310, x28 // Turn off big endianness for M mode before going into the trap handler // using '0x310' instead of mstatush because GCC doesn't recognize just mstatush GOTO_S_MODE @@ -91,7 +91,7 @@ GOTO_S_MODE li x28, 0xAABBCCDD li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0xAABBCCDD +sw x28, 0(x29) // value stored in memory as 0xAABBCCDD lw x30, 0(x29) // test load word, should read out 0xAABBCCDD sw x30, 0(t1) // test store word, should save 0xAABBCCDD @@ -111,7 +111,7 @@ addi a6, a6, 4 GOTO_M_MODE // Go back to M mode to be able to toggle SBE bit of mstatus li x28, 0x10 -csrs mstatush, x28 // turn on big endianness for S mode +csrs 0x310, x28 // turn on big endianness for S mode // using '0x310' instead of mstatush because GCC doesn't recognize just mstatush GOTO_S_MODE @@ -119,7 +119,7 @@ GOTO_S_MODE li x28, 0xAABBCCDD li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0xDDCCBBAA +sw x28, 0(x29) // value stored in memory as 0xDDCCBBAA lw x30, 0(x29) // test load word, should read out 0xAABBCCDD sw x30, 0(t1) // test store word, should save 0xDDCCBBAA @@ -142,7 +142,7 @@ GOTO_U_MODE li x28, 0xAABBCCDD li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0xAABBCCDD +sw x28, 0(x29) // value stored in memory as 0xAABBCCDD lw x30, 0(x29) // test load word, should read out 0xAABBCCDD sw x30, 0(t1) // test store word, should save 0xAABBCCDD @@ -170,7 +170,7 @@ GOTO_U_MODE li x28, 0xAABBCCDD li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0xDDCCBBAA +sw x28, 0(x29) // value stored in memory as 0xDDCCBBAA lw x30, 0(x29) // test load word, should read out 0xAABBCCDD sw x30, 0(t1) // test store word, should save 0xDDCCBBAA @@ -187,6 +187,9 @@ sb x30, 0(t1) // test store byte, should save 0xAA addi t1, t1, 4 addi a6, a6, 4 +//store_location: +//.fill + END_TESTS TEST_STACK_AND_DATA \ No newline at end of file