From c2021927cebd38fc0509251eeb78d3ab65a4757b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Feb 2023 17:54:48 -0600 Subject: [PATCH] Prep to fix gshare critical path. --- src/ifu/bpred/bpred.sv | 12 ++++++++---- src/ifu/bpred/btb.sv | 8 +++----- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index aee8c491..39ced3d9 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -94,9 +94,9 @@ module bpred ( logic RetD, JalD; logic RetE, JalE; logic BranchM, JumpM, RetM, JalM; + logic BranchW, JumpW, RetW, JalW; logic WrongBPRetD; - - logic [`XLEN-1:0] PCW; + logic [`XLEN-1:0] PCW, IEUAdrW; // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. @@ -152,8 +152,9 @@ module bpred ( .BTAF, .BTAD, .BTBPredInstrClassF({BTBJalF, BTBRetF, BTBJumpF, BTBBranchF}), .PredictionInstrClassWrongM, - .IEUAdrE, .IEUAdrM, - .InstrClassD({JalD, RetD, JumpD, BranchD}), .InstrClassE({JalE, RetE, JumpE, BranchE}), .InstrClassM({JalM, RetM, JumpM, BranchM})); + .IEUAdrE, .IEUAdrM, .IEUAdrW, + .InstrClassD({JalD, RetD, JumpD, BranchD}), .InstrClassE({JalE, RetE, JumpE, BranchE}), .InstrClassM({JalM, RetM, JumpM, BranchM}), + .InstrClassW({JalW, RetW, JumpW, BranchW})); if (!`INSTR_CLASS_PRED) begin : DirectClassDecode // This section is mainly for testing, verification, and PPA comparison. @@ -205,6 +206,7 @@ module bpred ( flopenrc #(2) InstrClassRegE(clk, reset, FlushE, ~StallE, {JalD, RetD}, {JalE, RetE}); flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, {JalE, RetE, JumpE, BranchE}, {JalM, RetM, JumpM, BranchM}); + flopenrc #(4) InstrClassRegW(clk, reset, FlushM, ~StallW, {JalM, RetM, JumpM, BranchM}, {JalW, RetW, JumpW, BranchW}); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); // branch predictor @@ -283,5 +285,7 @@ module bpred ( // **** Fix me assign InstrClassM = {JalM, RetM, JumpM, BranchM}; flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); + flopenrc #(`XLEN) IEUAdrWReg(clk, reset, FlushW, ~StallW, IEUAdrM, IEUAdrW); + endmodule diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 888287bc..362e416b 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -42,9 +42,11 @@ module btb #(parameter Depth = 10 ) ( input logic PredictionInstrClassWrongM, // BTB's instruction class guess was wrong input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb + input logic [`XLEN-1:0] IEUAdrW, input logic [3:0] InstrClassD, // Instruction class to insert into btb input logic [3:0] InstrClassE, // Instruction class to insert into btb - input logic [3:0] InstrClassM // Instruction class to insert into btb + input logic [3:0] InstrClassM, // Instruction class to insert into btb + input logic [3:0] InstrClassW ); logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex, PCWIndex; @@ -53,8 +55,6 @@ module btb #(parameter Depth = 10 ) ( logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; logic UpdateEn; - logic [3:0] InstrClassW; - logic [`XLEN-1:0] IEUAdrW; // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. @@ -103,6 +103,4 @@ module btb #(parameter Depth = 10 ) ( flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BTAF, BTAD); - flopenrc #(`XLEN+4) IEUAdrWReg(clk, reset, FlushW, ~StallW, {InstrClassM, IEUAdrM}, {InstrClassW, IEUAdrW}); - endmodule