From c0a4b7cb17d3e32a18893774af88114cdd9d6d30 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 3 May 2021 08:56:45 -0500 Subject: [PATCH] Fixed typo in ifu for bypassing branch predictor. Fixed missing signal name in local history predictor. --- wally-pipelined/src/ifu/ifu.sv | 2 +- .../src/ifu/localHistoryPredictor.sv | 126 +++++++++--------- 2 files changed, 64 insertions(+), 64 deletions(-) diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 1df3b5ff..37120505 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -184,7 +184,7 @@ module ifu ( assign BPPredDirWrongE = 1'b0; assign BTBPredPCWrongE = 1'b0; assign RASPredPCWrongE = 1'b0; - assign BPPredClassNonCFIWrong = 1'b0; + assign BPPredClassNonCFIWrongE = 1'b0; end endgenerate // The true correct target is PCTargetE if PCSrcE is 1 else it is the fall through PCLinkE. diff --git a/wally-pipelined/src/ifu/localHistoryPredictor.sv b/wally-pipelined/src/ifu/localHistoryPredictor.sv index 70e85562..8aaa85c0 100644 --- a/wally-pipelined/src/ifu/localHistoryPredictor.sv +++ b/wally-pipelined/src/ifu/localHistoryPredictor.sv @@ -30,74 +30,74 @@ module localHistoryPredictor #( parameter int m = 6, // 2^m = number of local history branches parameter int k = 10 // number of past branches stored - ) + ) (input logic clk, input logic reset, - input logic StallF, StallD, StallE, FlushF, FlushD, FlushE, + input logic StallF, StallD, StallE, FlushF, FlushD, FlushE, input logic [`XLEN-1:0] LookUpPC, output logic [1:0] Prediction, // update input logic [`XLEN-1:0] UpdatePC, input logic UpdateEN, PCSrcE, input logic [1:0] UpdatePrediction - + ); - logic [2**m-1:0][k-1:0] LHRNextF; - logic [k-1:0] LHRF, ForwardLHRNext; - logic [m-1:0] LookUpPCIndex, UpdatePCIndex; - logic [1:0] PredictionMemory; - logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF; - logic [1:0] UpdatePredictionF; + logic [2**m-1:0][k-1:0] LHRNextF; + logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext; + logic [m-1:0] LookUpPCIndex, UpdatePCIndex; + logic [1:0] PredictionMemory; + logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF; + logic [1:0] UpdatePredictionF; - assign LHRFNext = {PCSrcE, LHRF[k-1:1]}; - assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]}; - assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]}; + assign LHRFNext = {PCSrcE, LHRF[k-1:1]}; + assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]}; + assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]}; -// INCASE we do ahead pipelining -// SRAM2P1R1W #(m,k) LHR(.clk(clk)), -// .reset(reset), -// .RA1(LookUpPCIndex), // need hashing function to get correct PC address -// .RD1(LHRF), -// .REN1(~StallF), -// .WA1(UpdatePCIndex), -// .WD1(LHRENExt), -// .WEN1(UpdateEN), -// .BitWEN1(2'b11)); + // INCASE we do ahead pipelining + // SRAM2P1R1W #(m,k) LHR(.clk(clk)), + // .reset(reset), + // .RA1(LookUpPCIndex), // need hashing function to get correct PC address + // .RD1(LHRF), + // .REN1(~StallF), + // .WA1(UpdatePCIndex), + // .WD1(LHRENExt), + // .WEN1(UpdateEN), + // .BitWEN1(2'b11)); -genvar index; -generate + genvar index; + generate for (index = 0; index < 2**m; index = index +1) begin - flopenr #(k) LocalHistoryRegister(.clk(clk), - .reset(reset), - .en(UpdateEN && (index == UpdatePCIndex)), - .d(LHRFNext), - .q(LHRNextF[index])); + flopenr #(k) LocalHistoryRegister(.clk(clk), + .reset(reset), + .en(UpdateEN && (index == UpdatePCIndex)), + .d(LHRFNext), + .q(LHRNextF[index])); end -endgenerate + endgenerate -// need to forward when updating to the same address as reading. -// first we compare to see if the update and lookup addreses are the same -assign DoForwarding = LookUpPCIndex == UpdatePCIndex; -assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex]; + // need to forward when updating to the same address as reading. + // first we compare to see if the update and lookup addreses are the same + assign DoForwarding = LookUpPCIndex == UpdatePCIndex; + assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT // LHR referes to the address that the past k branches points to in the prediction stage // LHRE refers to the address that the past k branches points to in the exectution stage - SRAM2P1R1W #(k, 2) PHT(.clk(clk), - .reset(reset), - .RA1(ForwardLHRNext), - .RD1(PredictionMemory), - .REN1(~StallF), - .WA1(LHRFNext), - .WD1(UpdatePrediction), - .WEN1(UpdateEN), - .BitWEN1(2'b11)); + SRAM2P1R1W #(k, 2) PHT(.clk(clk), + .reset(reset), + .RA1(ForwardLHRNext), + .RD1(PredictionMemory), + .REN1(~StallF), + .WA1(LHRFNext), + .WD1(UpdatePrediction), + .WEN1(UpdateEN), + .BitWEN1(2'b11)); -assign DoForwardingPHT = LHRFNext == ForwardLHRNext; + assign DoForwardingPHT = LHRFNext == ForwardLHRNext; // register the update value and the forwarding signal into the Fetch stage // TODO: add stall logic *** @@ -115,24 +115,24 @@ assign DoForwardingPHT = LHRFNext == ForwardLHRNext; //pipeline for LHR flopenrc #(k) LHRFReg(.clk(clk), - .reset(reset), - .en(~StallF), - .clear(FlushF), - .d(ForwardLHRNext), - .q(LHRF)); -/* - flopenrc #(k) LHRDReg(.clk(clk), - .reset(reset), - .en(~StallD), - .clear(FlushD), - .d(LHRF), - .q(LHRD)); - + .reset(reset), + .en(~StallF), + .clear(FlushF), + .d(ForwardLHRNext), + .q(LHRF)); + /* + flopenrc #(k) LHRDReg(.clk(clk), + .reset(reset), + .en(~StallD), + .clear(FlushD), + .d(LHRF), + .q(LHRD)); + flopenrc #(k) LHREReg(.clk(clk), - .reset(reset), - .en(~StallE), - .clear(FlushE), - .d(LHRD), - .q(LHRE)); -*/ + .reset(reset), + .en(~StallE), + .clear(FlushE), + .d(LHRD), + .q(LHRE)); + */ endmodule